Patent US3735257A successfully refreshed from Google Patents.
US3735257A
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Tachometer processing circuit using logic device to generate equal width pulses
Assignee: Motors Liquidation Co
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Filing: 1971-10-12
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Granted: 1973-05-22
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Expires: 1991-10-12
Abstract
Abstract A voltage level analog of the frequency of a rotating member is developed by a tachometer processing circuit using a NAND logic device. A first pulse train related in frequency with the frequency of the rotating member is applied to an RC timing circuit to control a transistor switching device to develop a second pulse train at the transistor output at the same frequency as the first pulse train, but having pulse widths differing by a fixed predetermined amount of dwell. The second pulse train and an inverted version of the first pulse train are applied to a NAND logic device to develop a pulse train having pulses with widths equal to the dwell by which pulses in the second train exceed pulses in the first train. The pulses developed by the NAND logic device are averaged by an RC filter to provide a DC analog of frequency.
Inventors
- 👤 B Roesner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 01:49
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/4802; G01P3/4805; G01R; G01R23/00; G01R23/02; G01R23/06; G01R23/09
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
193 words
A circuit for measuring the frequency of pulses in a pulse train, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said pulse train; a voltage controlled switching device having an input and an output; means connecting the input of said switching device with said timing circuit, said timing circuit controlling said switching device such that a first pulse is developed at the output of said switching device for each pulse in said pulse train, each of said first pulses developed at the output of said switching device having a duration differing from the duration of the associated pulse of the pulse train by a fixed predetermined amount of dwell set by said timing circuit; a logic device coupled with the output of said switching device and said pulse train to generate a second pulse having a width related to said predetermined dwell in response to each of said first pulses; and means coupled with said logic device for summing all of said second pulses and providing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
Claim 2
Dependent Claim
193 words
A circuit for measuring the frequency of pulses in a pulse train, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said pulse train; a voltage controlled switching device having an input and an output; means connecting the input of said switching device with said timing circuit, said timing circuit controlling said switching device such that a first pulse is developed at the output of said switching device for each pulse in said pulse train, each of said first pulses developed at the output of said switching device having a duration differing from the duration of the associated pulse of the pulse train by a fixed predetermined amount of dwell set by said timing circuit; a logic device coupled with the output of said switching device and said pulse train to generate a second pulse having a width related to said predetermined dwell in response to each of said first pulses; and means coupled with said logic device for summing all of said second pulses and providing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
Claim 3
Dependent Claim
206 words
A circuit for measuring the frequency of a first train of substantially rectangular voltage pulses, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said first train of voltage pulses; a voltage controlled switching device having an input and an output; means connecting the input of said switching device with said timing circuit, said timing circuit controlling said switching device such that a second train of substantially rectangular voltage pulses at the frequency to be measured is developed at the output of said switching device, each pulse in said second train of voltage pulses having a dwell greater than the associated pulse in said first train of voltage pulses by a fixed predetermined amount set by said timing circuit; a logic device coupled with said second train of voltage pulses and said first train of voltage pulses providing a signal pulse having a duration proportional to said predetermined dwell for each pulse in said second train of voltage pulses; and means coupled with said logic device for summing all of said signal pulses provided by said logic device and developing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
Claim 4
Dependent Claim
206 words
A circuit for measuring the frequency of a first train of substantially rectangular voltage pulses, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said first train of voltage pulses; a voltage controlled switching device having an input and an output; means connecting the input of said switching device with said timing circuit, said timing circuit controlling said switching device such that a second train of substantially rectangular voltage pulses at the frequency to be measured is developed at the output of said switching device, each pulse in said second train of voltage pulses having a dwell greater than the associated pulse in said first train of voltage pulses by a fixed predetermined amount set by said timing circuit; a logic device coupled with said second train of voltage pulses and said first train of voltage pulses providing a signal pulse having a duration proportional to said predetermined dwell for each pulse in said second train of voltage pulses; and means coupled with said logic device for summing all of said signal pulses provided by said logic device and developing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
Claim 5
Dependent Claim
207 words
A circuit for measuring the frequency of pulses in a pulse train, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said pulse train; a transistor switching device having an input and an output; means connecting the input of said transistor switching device with said timing circuit, said timing circuit controlling said transistor switching device such that a first pulse is developed at the output of said transistor switching device for each pulse in said pulse train, each of said first pulses developed at the output of said transistor switching device having a width differing from the width of the associated pulse of the pulse tRain by a fixed predetermined amount of dwell set by said timing circuit; means connected with said pulse train for inverting said pulse train; a NAND logic device coupled with said transistor switching device and the inverted pulse train providing a second pulse having a width proportional to said predetermined dwell in response to each of said first pulses; and means coupled with said NAND logic device for summing all of said second pulses and providing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
Claim 6
Dependent Claim
207 words
A circuit for measuring the frequency of pulses in a pulse train, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said pulse train; a transistor switching device having an input and an output; means connecting the input of said transistor switching device with said timing circuit, said timing circuit controlling said transistor switching device such that a first pulse is developed at the output of said transistor switching device for each pulse in said pulse train, each of said first pulses developed at the output of said transistor switching device having a width differing from the width of the associated pulse of the pulse tRain by a fixed predetermined amount of dwell set by said timing circuit; means connected with said pulse train for inverting said pulse train; a NAND logic device coupled with said transistor switching device and the inverted pulse train providing a second pulse having a width proportional to said predetermined dwell in response to each of said first pulses; and means coupled with said NAND logic device for summing all of said second pulses and providing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
Claim 7
Dependent Claim
188 words
A circuit for measuring the frequency of a symmetric square-wave voltage, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said square-wave voltage; a voltage controlled transistor switching device having an input and an output; means connecting the input of said transistor switching device with said timing circuit, said timing circuit controlling said transistor switching device such that a square-wave at the frequency to be measured is developed at the output of said transistor switching device having a waveform asymmetric in time in each cycle by a fixed predetermined amount of dwell set by said timing circuit; means connected with said symmetric square-wave voltage for inverting said symmetric square-wave voltage; a NAND logic device coupled with said transistor switching device and the inverted symmetric square-wave voltage providing a pulse in each cycle having a duration proportional to said predetermined dwell; and means coupled with said NAND logic device for summing all of said pulses provided by said NAND logic device and developing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
Claim 8
Dependent Claim
188 words
A circuit for measuring the frequency of a symmetric square-wave voltage, comprising: a resistor; a capacitor; means interconnecting said resistor and said capacitor in a timing circuit for connection with said square-wave voltage; a voltage controlled transistor switching device having an input and an output; means connecting the input of said transistor switching device with said timing circuit, said timing circuit controlling said transistor switching device such that a square-wave at the frequency to be measured is developed at the output of said transistor switching device having a waveform asymmetric in time in each cycle by a fixed predetermined amount of dwell set by said timing circuit; means connected with said symmetric square-wave voltage for inverting said symmetric square-wave voltage; a NAND logic device coupled with said transistor switching device and the inverted symmetric square-wave voltage providing a pulse in each cycle having a duration proportional to said predetermined dwell; and means coupled with said NAND logic device for summing all of said pulses provided by said NAND logic device and developing an average voltage related thereto, thereby providing a voltage level analog of the frequency being measured.
References Cited (Backward Citations)
US3497719A
Cited
US3585400A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-21 | 1976-11-20 | 1977-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-21 | 1980-11-20 | 1981-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-21 | 1984-11-20 | 1985-05-22 | $7700.00 | Window Closed / Lapsed |