Error checked incrementing circuit

Claim 2

A self-checking circuit for incrementing a data word obtained from a data word source comprising: a plurality of serially connected adder stages having input terminals connected to corresponding output terminals of said data word source, a plurality of output terminals connected to a data utilization circuit and transition detecting means individual to said stages for generating at output terminals thereof output signals defining ''''0'''' to ''''1'''' transitions in said adder stages when a data word is applied to said input terminals of said incrementing circuit; circuit means connected to said output terminals of said detecting means for generating a first signal if a single transition of the type above defined occurs during an incrementing function and for generating signals predicting the parity of the data word occurring at said output terminals of said adder stages.

Claim 3

A circuit for incrementing a data word in accordance with claim 1 wherein said circuit means comprises first and second one-out-of-n detecting means for generating an output signal of a first character if a single transition of the type above defined is to occur in the stages to which said one-out-of-n detecting means is connected, said first one-out-of-n detecting means being connected to the odd numbered ones of said adder stages and said second detecting means being connected to the even numbered ones of said adder stages, and means connected to the output terminals of said one-out-of-n detecting means for generating an output signal of a first character if a transition is to occur in an odd numbered one of said adder stages and a signal of a second character if a transition is to occur in an even numbered one of said adder stages.

Claim 4

A circuit for incrementing a data word obtained from a data word source by a count of one comprising: a plurality of serially connected adder stages arranged in two groups identified as even numbered stages and odd numbered stages, respectively, having input terminals connected to corresponding output terminals of said data word source, a plurality of output terminals connected to a data utilization circuit and transition detecting means individual to said adder stages for generating at output terminals thereof output signals indicating that a transition from a ''''0'''' binary state to a ''''1'''' binary state is to occur in a connected adder stage; and fault detecting means connected to said output terminals of said transition detecting means for generating a fault signal if said transition detecting means indicate that no transition is to occur or that a transition is to occur in both said odd numbered and said even numbered stages and parity generating means connected to said output terminals of said transition detecting means and to the parity bit output terminal of said data word source for generating a predicted parity signal for the data word appearing at the output terminals of said adder stages.

Claim 5

A circuit for incrementing a data word obtained from a data word source by a count of one comprising: a plurality of serially connected adder stages arranged in two groups identified as even numbered stages and odd numbered stages, respectively, having input terminals connected to corresponding output terminals of said data word source, a plurality of output terminals connected to a data utilization circuit and transition detecting means individual to said adder stages for generating at output terminals thereof output signals indicating that a transition from a ''''0'''' binary state to a ''''1'''' binary state is to occur in a connected adder stage; and fault detecting means connected to said output terminals of said transition detecting means for generating a fault signal if said transition detecting means indicate that no transition is to occur or that a transition is to occur in both said odd numbered and said even numbered stages and parity generating means connected to said output terminals of said transition detecting means and to the parity bit output terminal of said data word source for generating a predicted parity signal for the data word appearing at the output terminals of said adder stages.

Claim 6

A circuit for incrementing a data word in accordance with claim 3 comprising: second parity generating means connected to said data utilization circuit for generating a parity signal for a data word occurring at said output terminals of said incrementing circuit and a comparator circuit for comparing said predicted parity signal and said parity signal generated by said parity generating means and for generating a fault signal if said parity signals are not identical.

Claim 7

A self-checking circuit for incrementing a data word obtained from a data word source comprising: a plurality of serially connected adder stages having input terminals connected to corresponding output terminals of said data word source and a plurality of output terminals; a data utilization circuit connectable to said output terminals; the odd numbered oNes of said adder stages comprising first transition detecting means for generating signals indicating that a single ''''0'''' to ''''1'''' transition should occur in said connected adder stages during the incrementing of said data word obtained from said data word source; the even numbered ones of said adder stages comprising a second transition detecting circuit for generating signals indicating that a single ''''0'''' to ''''1'''' transition should occur in said connected adder stages during the incrementing of said data word obtained from said data word source; first parity generating means connected to the output terminals of said first and second second transition detecting circuits and responsive to said output signals therefrom and connected to the parity bit output terminal of said data word source for generating a predicted parity bit for the incremented data word; second parity generating means connected to said data utilization circuit for generating a parity signal for a data word presented to said data utilization circuit from said incrementing circuit; means for comparing said predicted parity signal and said parity signal from said second parity generating means and for generating a trouble signal when said parity signals are not identical; and circuit means connected to said output terminals of said first and said second transition detecting means for generating error signals if said first and said second transition detecting means generate identical output signals during said incrementing of said data word.

Claim 8

A self-checking circuit for incrementing a data word obtained from a data word source comprising: a plurality of serially connected adder stages having input terminals connected to corresponding output terminals of said data word source and a plurality of output terminals; a data utilization circuit connectable to said output terminals; the odd numbered oNes of said adder stages comprising first transition detecting means for generating signals indicating that a single ''''0'''' to ''''1'''' transition should occur in said connected adder stages during the incrementing of said data word obtained from said data word source; the even numbered ones of said adder stages comprising a second transition detecting circuit for generating signals indicating that a single ''''0'''' to ''''1'''' transition should occur in said connected adder stages during the incrementing of said data word obtained from said data word source; first parity generating means connected to the output terminals of said first and second second transition detecting circuits and responsive to said output signals therefrom and connected to the parity bit output terminal of said data word source for generating a predicted parity bit for the incremented data word; second parity generating means connected to said data utilization circuit for generating a parity signal for a data word presented to said data utilization circuit from said incrementing circuit; means for comparing said predicted parity signal and said parity signal from said second parity generating means and for generating a trouble signal when said parity signals are not identical; and circuit means connected to said output terminals of said first and said second transition detecting means for generating error signals if said first and said second transition detecting means generate identical output signals during said incrementing of said data word.