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US3567916A
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Apparatus for parity checking a binary register
Assignee: United States Department of the Army
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Filing: 1969-01-22
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Granted: 1971-03-02
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Expires: 1989-01-22
Abstract
Abstract The parity of a shift register and a binary counter are checked by predicting what the parity change should be and comparing this with what the actual parity is. In checking a shift register the parity of the next state is determined by sensing the number of ''''ones'''' entering and leaving the register. This gives the change in the number of ''''ones'''' in the register; therefore, letting one know whether the parity will change or not. The same is done in checking a binary counter. All the consecutive ''''ones'''' (starting with the lowest order stage) are counted. With this any change in the parity of the next count can be predicted.
Inventors
- 👤 James M Fulton Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/28; H; H03; H03K; H03K21/00; H03K21/40
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
271 words
An error checking system for a binary counter comprising a binary counter having a plurality of stages, a parity tree having inputs connected to the stages so as to produce at its output the parity of said counter, a first exclusive OR circuit having a first input connected to the output of said parity tree, a next state indicator having an output and a plurality of inputs, the inputs of said indicator being connected to the stages of the binary counter, said next state indicator being so constructed as to produce a logic 1 output only when the counter has an even number of consecutive stages having a logic 1 starting with the lowest order stage, said next state indicator further being constructed so that it will produce a logic 0 on its output when the binary counter has an odd number of said consecutive stages, means connecting said output of said next state indicator to a second input of said first exclusive OR circuit, a register means having an input connected to an output of said first exclusive OR circuit for storing the information obtained from the first circuit during the next count of the binary counter, a second exclusive OR circuit having first and second inputs connected respectively to an output of said register and to the output of the parity tree, said second exclusive OR circuit comparing the parity now present on the counter with the information stored by the register on the previous count of the counter, and said second exclusive OR circuit having an output which will indicate a fault if it is a logic 1.
Claim 2
Dependent Claim
271 words
An error checking system for a binary counter comprising a binary counter having a plurality of stages, a parity tree having inputs connected to the stages so as to produce at its output the parity of said counter, a first exclusive OR circuit having a first input connected to the output of said parity tree, a next state indicator having an output and a plurality of inputs, the inputs of said indicator being connected to the stages of the binary counter, said next state indicator being so constructed as to produce a logic 1 output only when the counter has an even number of consecutive stages having a logic 1 starting with the lowest order stage, said next state indicator further being constructed so that it will produce a logic 0 on its output when the binary counter has an odd number of said consecutive stages, means connecting said output of said next state indicator to a second input of said first exclusive OR circuit, a register means having an input connected to an output of said first exclusive OR circuit for storing the information obtained from the first circuit during the next count of the binary counter, a second exclusive OR circuit having first and second inputs connected respectively to an output of said register and to the output of the parity tree, said second exclusive OR circuit comparing the parity now present on the counter with the information stored by the register on the previous count of the counter, and said second exclusive OR circuit having an output which will indicate a fault if it is a logic 1.
Claim 3
Dependent Claim
221 words
An error checking system for a binary shift register comprising a binary shift register having an input, output, and a plurality of stages, first and second one-stage counters, said first counter having its input connected to the input of said shift register, said second counter having its input connected to the output of said shift register, an exclusive OR circuit having first and second inputs connected to outputs of said first and second counters, a parity tree having inputs connected to the stages of said shift register and having an output which is the parity of the information in said register, a storage register having an input connected to the output of said parity tree so as to store the parity of the previous condition of the shift register, a second exclusive OR circuit having first and second inputs connected respectively to the outputs of said first exclusive OR circuit and said storage register so that the output of said second exclusive OR circuit is a predicted parity of the present condition of said shift register, a third exclusive OR circuit having first and second inputs connected respectively, to the outputs of the parity tree and the second exclusive OR circuit, and said third exclusive OR circuit having an output which will indicate a fault if it is a logic 1.
Claim 4
Dependent Claim
221 words
An error checking system for a binary shift register comprising a binary shift register having an input, output, and a plurality of stages, first and second one-stage counters, said first counter having its input connected to the input of said shift register, said second counter having its input connected to the output of said shift register, an exclusive OR circuit having first and second inputs connected to outputs of said first and second counters, a parity tree having inputs connected to the stages of said shift register and having an output which is the parity of the information in said register, a storage register having an input connected to the output of said parity tree so as to store the parity of the previous condition of the shift register, a second exclusive OR circuit having first and second inputs connected respectively to the outputs of said first exclusive OR circuit and said storage register so that the output of said second exclusive OR circuit is a predicted parity of the present condition of said shift register, a third exclusive OR circuit having first and second inputs connected respectively, to the outputs of the parity tree and the second exclusive OR circuit, and said third exclusive OR circuit having an output which will indicate a fault if it is a logic 1.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |