Monolithic integrated structure including fabrication and packaging therefor
Abstract
Abstract A method of making a monolithic integrated semiconductor structure that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object of mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other importance aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure.
Inventors
- 👤 B Agusta
- 👤 P Bardell
- 👤 P Castrucci
- 👤 R Henle
- 👤 R Pecorato
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-07 | 1976-11-06 | 1977-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-07 | 1980-11-06 | 1981-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-07 | 1984-11-06 | 1985-05-08 | $7700.00 | Window Closed / Lapsed |