Circuit for avoiding false lock

Claim 2

In a system comprising two generators for producing identical pseudo-random sequences of a given length; said generators each comprising a shift register having a plurality of stages and a set of feedback connections from a number of said stages through modulo 2 adders to the input stage of the shift register; said generators being adapted to produce a different pseudo-random sequence of the same length when said feedback connections are appropriately altered; means for altering said feedback connections of one of said generators to produce said different pseudo-random sequence when a predetermined binary word exists in said one generator; and means for altering the feedback connections of the other one of said generators to produce said different pseudo-random sequence after said feedback connections have been altered in said one generator and when said predetermined binary word exists in said other generator.

Claim 3

A system as defined in claim 1 wherein said means for altering the feedback connections of said one generator are further adapted to return said feedback connections to said set of feedback connections after a predetermined time and when said predetermined binary word exists in said one generator and the feedback connections comprise said altered feedback connections; and wherein the means for altering the feedback connections of said other generator are further adapted to return said feedback connections to said set of feedback connections after a predetermined time and when said predetermined binary word exists in said other generator and the feedback connections comprise said altered feedback connections.

Claim 4

A system as defined in claim 2 wherein said first generator comprises eleven serially connected flip-flops, each flip-flop comprising an input terminal and an output terminal; and further comprising three modulo 2 adders, each adder comprising two input terminals and an output terminal; and feedback selector logic means comprising two input terminals, an output terminal, and a control terminal; the output terminals of said sixth and eighth flip-flops being connected respectively to the first and second input terminals of one of said modulo 2 adders; the output terminals of said ninth and tenth flip-flops being connected respectively to the first and second input terminals of said feedback selector logic means; the output terminal of the eleventh flip-flop being connected to one input terminal of a second modulo 2 adder, and the output terminal of said feedback selector logic means being connected to the second input terminal of said second modulo 2 adder; the output terminals of said first and second modulo 2 adders being connected respectively to the first and second input terminals of said third modulo 2 adder, the output terminal of said third modulo 2 adder being connected to the input terminal of the first flip-flop; and the control terminal of said feedback selector logic means being connected to means for detecting said predetermined binary word in said first generator; wherein said feedback selector logic means comprises said means for altering the feedback connections of said one generator; whereby said feedback connections of said one generator alternate between feedback from sixth, eighth, ninth and eleventh flip-flop output terminals and feedback from said sixth, eighth, tenth and eleventh flip-flop output terminals; and wherein sAid second generator comprises a further eleven serially connected flip-flops, each further flip-flop comprising an input terminal and an output terminal; and further comprising three further modulo 2 adders, each further adder comprising two input terminals and an output terminal; and a further feedback selector logic means comprising two input terminals, an output terminal and a control terminal; the output terminals of said further sixth and eighth flip-flops being connected respectively to the first and second input terminals of one of said further modulo 2 adders; the output terminals of said further ninth and tenth flip-flops being connected respectively to the first and second input terminals of said further feedback selector logic means; the output terminal of the further eleventh flip-flop being connected to one input terminal of a second further modulo 2 adder, and the output terminal of said further feedback selector logic means being connected to the second input terminal of said further second modulo 2 adder; the output terminals of said further first and second modulo 2 adders being connected respectively to the first and second input terminals of said further third modulo 2 adder, the output terminal of said further third modulo 2 adder being connected to the input terminal of the further first flip-flop; and the control terminal of said further feedback selector logic means being connected to further means for detecting said predetermined word in said second generator; wherein said further feedback selector logic means comprises said means for altering the feedback connections of said second generator; whereby said feedback connections of said second generator alternate between feedback from said sixth, eighth, ninth and eleventh flip-flop output terminals and feedback from said sixth, eighth, tenth and eleventh flip-flop output terminals.

Claim 5

A system as defined in claim 3 wherein said means for detecting said predetermined binary word in said first generator comprises a first 11-input AND gate, the output terminals of each of said eleven flip-flops being connected respectively to a different input of said AND gate; and wherein said means for detecting said predetermined binary word in said second generator comprises a second 11-input AND gate, the output terminals of each of said further eleven flip-flops being connected respectively to a different input of said second AND gate; and further comprising a time sharing sync pulse generator having three input terminals and two output terminals; and two D flip-flops, each having a D input terminal and a clock pulse input terminal, and Q and Q output terminals; the output terminals of said first and second AND gates being connected respectively to the first and second input terminals of said time sharing sync pulse generator; and a source of square waves being connected to the third input terminal of said time sharing sync pulse generator; one output terminal of said sync pulse generator being connected to the clock pulse terminal of one of said D flip-flops, the other output terminal of said sync pulse generator being connected to the clock pulse terminal of said other D flip-flop; the Q output terminal of said first D flip-flop being connected to the control terminal of said feedback selector logic means and the Q output terminal of said second D flip-flop being connected to the control terminal of said further feedback selector logic means, the Q output terminal of said first D flip-flop being connected to the D input terminal of said first D flip-flop, and the Q output terminal of said first D flip-flop being further connected to the D input terminal of said second D flip-flop; whereby clock pulses at said square wave rate and synchronized with the output of said first AND gate are provided to the clock pulse input terminal of said first D flip-flop; and clock pulses at said square wave rate and synchronized witH the output of said second AND gate are provided to the clock pulse input terminal of said second D flip-flop.