Pulse compression code sequencing system

Claim 2

A pulse transmission and receiving system comprising: input means for receiving signal pulses to be coded and returned codes to be decoded; coding means coupled to said input means for alternately providing a first code and a second code from the signal pulses before the transmission thereof, said coding means comprising a first code portion for providing coded pulses and a second code portion for providing coded pulses differing from the coded pulses of said first code portion, and means for cyclically permuting the coded pulses from said first code portion with the coded pulses of said second code portion in synchronism with the signal pulses in order to produce the first and second codes to be transmitted; and decoding means coupled to said input means for alternately decoding the first code and the second code upon reception thereof.

Claim 3

The system as defined in claim 1 wherein: said decoding means comprises a first decode portion for decoding the coded pulses provided by said first code portion and a second decode portion for decoding the coded pulses provided by said second code portion.

Claim 4

In apparatus for transmitting and receiving pulses in a sequential order, comprising: pulse coding means including a coding section and a decoding section, first switching means coupled to said pulse coding means for alternately applying the transmitted and received pulses to the coding section and decoding section, respectively, in said pulse coding means, and second switching means coupled to said pulse coding means for providing alternate codes from the pulse from said pulse coding means.

Claim 5

In apparatus for transmitting and receiving pulses in a sequential order, comprising: pulse coding means including a coding section and a decoding section, first switching means coupled to said pulse coding means for alternately applying the transmitted and received pulses to the coding section and decoding section, respectively, in said pulse coding means, and second switching means coupled to said pulse coding means for providing alternate codes from the pulse from said pulse coding means.

Claim 6

The apparatus as defined in claim 3 further comprising a source of pulses to be transmitted, said pulse coding means being coupled to said source of pulses for cyclic permuting the transmitted and received codes in said coding means.

Claim 7

The apparatus as defined in claim 4 further including a memory system coupled to said pulse coding means to store the decoded pulses.

Claim 8

A pulse sequencing system comprising: a plurality of series coupled tapped delay lines, each said delay line of said plurality having a plurality of parallel output circuits; a first adder, said first adder having a plurality of input circuits coupled to the plurality of output circuits of a first selected one of said plurality of delay lines, said first adder having an output circuit; a second adder, said second adder having a plurality of input circuits coupled to the plurality of output circuits of a second selected one of said plurality of delay lines, said second adder having an output circuit; a third adder, said third adder having a plurality of input circuits coupled to the plurality of output circuits of the remaining ones of said plurality of delay lines, said third adder having an output circuit; a fourth adder, said fourth adder having a first input circuit coupled to the output circuit of said third adder and a second input circuit, said fourth adder having an output circuit coupled to a transmit device; and first switching means, said first switching means having: a first input circuit coupled to the output circuit of said first addEr, a second input circuit coupled to the output circuit of said second adder, and an output circuit coupled to the transmit device, said first switching means being capable of alternately coupling said first and said second adder to said fourth adder.

Claim 9

A pulse sequencing system comprising: a plurality of series coupled tapped delay lines, each said delay line of said plurality having a plurality of parallel output circuits; a first adder, said first adder having a plurality of input circuits coupled to the plurality of output circuits of a first selected one of said plurality of delay lines, said first adder having an output circuit; a second adder, said second adder having a plurality of input circuits coupled to the plurality of output circuits of a second selected one of said plurality of delay lines, said second adder having an output circuit; a third adder, said third adder having a plurality of input circuits coupled to the plurality of output circuits of the remaining ones of said plurality of delay lines, said third adder having an output circuit; a fourth adder, said fourth adder having a first input circuit coupled to the output circuit of said third adder and a second input circuit, said fourth adder having an output circuit coupled to a transmit device; and first switching means, said first switching means having: a first input circuit coupled to the output circuit of said first addEr, a second input circuit coupled to the output circuit of said second adder, and an output circuit coupled to the transmit device, said first switching means being capable of alternately coupling said first and said second adder to said fourth adder.

Claim 10

The pulse sequencing system as defined in claim 6 wherein said plurality of series coupled tapped delay lines includes a further plurality of parallel output circuits and further comprising: a fifth adder, said fifth adder having a plurality of input circuits coupled to the further plurality of output circuits of a first selected one of said plurality of delay lines, said fifth adder having an output circuit; a sixth adder, said sixth adder having a plurality of input circuits coupled to the further plurality of output circuits of a second selected one of said plurality of delay lines, said sixth adder having an output circuit; a seventh adder, said seventh adder having a plurality of input circuits coupled to the further plurality of output circuits of the remaining ones of said plurality delay lines, said seventh adder having an output circuit; an eighth adder, said eighth adder having a first input circuit coupled to the output circuit of said seventh adder and a second input circuit, said eighth adder having an output circuit coupled to a transmit device; and second switching means, said second switching means having: a first input circuit coupled to the output circuit of said fifth adder, a second input circuit coupled to the output circuit of said sixth adder, and an output circuit coupled to the transmit device, said second switching means being capable of alternately coupling said fifth and said sixth adder to said eighth adder.

Claim 11

A pulse sequencing system comprising: first delay means for receiving a first train of pulses and a second train of pulses, said means including a first plurality of parallel output means and a second plurality of parallel output means; second delay means for receiving the first train of pulses and the second train of pulses, said means having a first plurality of parallel output means and a second plurality of parallel output means; a first adder; first switching means coupled to said first plurality of parallel output means of said first delay means and said first plurality of parallel outputs of said second delay means, said switching means being capable of applying said first train of pulses and said second train of pulses to said first adder in a first predetermined order and for applying said second train of pulses and said first train of pulses to said first adder in a second predetermined order; a second adder; and second switching means coupled to said second plurality of parallel output means of said first delay means and to said second plurality of parallel output means of said second delay means and said switching means being capable of applying said first train of pulses and said second train of pulses to said second adder in the first predetermined order and of applying said second train of pulses and said first train of pulses to said second adder in the second predetermined order.

Claim 12

A pulse sequencing system comprising: first delay means for receiving a first train of pulses and a second train of pulses, said means including a first plurality of parallel output means and a second plurality of parallel output means; second delay means for receiving the first train of pulses and the second train of pulses, said means having a first plurality of parallel output means and a second plurality of parallel output means; a first adder; first switching means coupled to said first plurality of parallel output means of said first delay means and said first plurality of parallel outputs of said second delay means, said switching means being capable of applying said first train of pulses and said second train of pulses to said first adder in a first predetermined order and for applying said second train of pulses and said first train of pulses to said first adder in a second predetermined order; a second adder; and second switching means coupled to said second plurality of parallel output means of said first delay means and to said second plurality of parallel output means of said second delay means and said switching means being capable of applying said first train of pulses and said second train of pulses to said second adder in the first predetermined order and of applying said second train of pulses and said first train of pulses to said second adder in the second predetermined order.

Claim 13

The pulse sequencing system as defined in claim 8 wherein said first and said second delay means comprises tapped delay lines.

Claim 14

A pulse compression code sequencing system for providing pulse codes to be coded and transmitted during a transmit mode of operation and received and decoded during a receive mode of operation in order to reduce sidelobes, comprising: input means for receiving signal pulses to be coded for transmission and received codes to be decoded; coding means coupled to said input means, said coding means having a coding section for developing first and second pulse codes from the signal pulses and a decoding section for decoding the received first and second pulse codes; first switching means coupled to said input means and said coding means for alternately applying the signal pulses to The coding section and the received codes to the decoding section; second switching means coupled to said coding means for alternately providing the first and second pulse codes to be transmitted; and means coupled to said decoding section for combining the decoded first and second pulse codes in order to reduce the sidelobes.

Claim 15

A pulse compression code sequencing system for providing pulse codes to be coded and transmitted during a transmit mode of operation and received and decoded during a receive mode of operation in order to reduce sidelobes, comprising: input means for receiving signal pulses to be coded for transmission and received codes to be decoded; coding means coupled to said input means, said coding means having a coding section for developing first and second pulse codes from the signal pulses and a decoding section for decoding the received first and second pulse codes; first switching means coupled to said input means and said coding means for alternately applying the signal pulses to The coding section and the received codes to the decoding section; second switching means coupled to said coding means for alternately providing the first and second pulse codes to be transmitted; and means coupled to said decoding section for combining the decoded first and second pulse codes in order to reduce the sidelobes.

Claim 16

The pulse compression code sequencing system of claim 10 further including: third switching means coupled to said decoding section for alternately providing the received first and second pulse codes to be decoded; and wherein said coding means comprises a plurality of series coupled tapped delay lines, a first plurality of adder means selectively coupled between said plurality of tapped delay lines and said second switching means for providing the first and second pulse codes whereby the second pulse code is a cyclic permutation of the first pulse code by a few bits, a second plurality of adder means selectively coupled between said plurality of tapped delay lines and said third switching means for providing the decoded first and second pulse codes.

Claim 17

The pulse compression code sequencing system of claim 10 wherein said coding means comprises: a first adder in said coding section for providing the first and second pulse codes to be transmitted; a second adder in said decoding section for providing the decoded first and second pulse codes; first and second tapped delay lines selectively coupled to said first and second adders and being responsive to a first condition of said second switching means for sequentially applying a first train of pulses from said first tapped delay line and a second train of pulses from said second tapped delay line to said first adder in a first predetermined order and being further responsive to a second condition of said second switching means for sequentially applying the second train of pulses and the first train of pulses to said first adder in a second predetermined order for the subsequent transmission thereof, said first and second tapped delay lines being still further responsive to the first and second conditions of said second switching means during the receive mode of operation for alternately applying the first and second predetermined orders of the first and second trains of pulses to said second adder.

Claim 18

The pulse compression code sequencing system of claim 10 further including: third switching means coupled to said decoding section for alternately providing the received first and second pulse codes to be decoded; and wherein said coding means comprises a tapped delay line, a first plurality of adder means selectively coupled between said tapped delay line and said second switching means for providing the first and second pulse codes, whereby the first and second pulse codes are each composed of odd and even numbered bits with the odd bits of the second code respectively corresponding in polarity to the odd bits of the first code and the even bits of the second code respectively having the opposite polarity from those of the first code, and a second plurality of adder means selectively coupled between said tapped delay line and said third switching means for providing the decoded first and second pulse codes.