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US3727145A
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Digital modulo complementary phase detector
Assignee: Collins Radio Co
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Filing: 1971-11-03
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Granted: 1973-04-10
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Expires: 1991-11-03
Abstract
Abstract A digital modulo complementary noncontinuous phase detector for input signals conditioned to a pulse density representation. The detector uses one error counter and a modulo counter wherein, with counter operation, numbers added are represented as a pulse train that the error counter accumulates with the pulse total representative of numerical magnitude and error counter direction represents sign.
Inventors
- 👤 D Huntsinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:51
CPC Classifications
G; G01; G01R; G01R25/00; G01R25/08
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
177 words
A noncontinuous digital modulo complementary phase detector comprising: a. gating control means, b. error counter means, c. overflow memory means connected to said error counter means, d. modulo counter means, e. error output gating means, f. reference frequency means, g. decoder means interconnected with said reference frequency means and applying two phase gate signals per input signal frequency to said gating control means, h. differentiator means interconnected to receive an input signal and apply a differentiated input signal to said gating control means, i. said gating control means being responsive to application of said gate signals and applying clock signals from said reference frequency means to said error counter means until receipt of a differentiated input signal during said gate period, j. means interconnecting said error counter means and said modulo counter means to said error output gating means and responsive to an error gate signal to produce an error count output, and k. up/down memory means interconnected with said overflow memory means and said error output gating means for indicating sign of said error count output.
Claim 2
Dependent Claim
177 words
A noncontinuous digital modulo complementary phase detector comprising: a. gating control means, b. error counter means, c. overflow memory means connected to said error counter means, d. modulo counter means, e. error output gating means, f. reference frequency means, g. decoder means interconnected with said reference frequency means and applying two phase gate signals per input signal frequency to said gating control means, h. differentiator means interconnected to receive an input signal and apply a differentiated input signal to said gating control means, i. said gating control means being responsive to application of said gate signals and applying clock signals from said reference frequency means to said error counter means until receipt of a differentiated input signal during said gate period, j. means interconnecting said error counter means and said modulo counter means to said error output gating means and responsive to an error gate signal to produce an error count output, and k. up/down memory means interconnected with said overflow memory means and said error output gating means for indicating sign of said error count output.
Claim 3
Dependent Claim
27 words
A noncontinuous digital modulo complementary phase detector as defined by claim 1 wherein said differentiator means comprises a limiter and a differentiator synchronized with said clock signals.
Claim 4
Dependent Claim
52 words
A noncontinuous digital modulo complementary phase detector as defined by claim 1 wherein said decoder means comprises a reference divider for developing a plurality of binary coded decimal outputs and a decoder circuit means responsive to said binary coded decimal outputs and generating said phase gate signals and said error gate signal.
Claim 5
Dependent Claim
90 words
A noncontinuous digital modulo complementary phase detector as defined by claim 1 wherein said modulo counter means includes a two input NAND gate, a modulo counter, a set/reset modulo counter control, means connecting the set output of said modulo counter control to one input of said gate, means connecting said reference frequency to the other input of said gate, means connecting the output of said gate to the input of said modulo counter, and means connecting the output of said modulo counter to the reset input of said counter control.
Claim 6
Dependent Claim
144 words
A noncontinuous digital modulo complementary phase detector as defined by claim 1 wherein said differentiator means comprises a limiter and a differentiator synchronized with said clock signals; said decoder means comprises a reference divider for developing a plurality of binary coded decimal outputs and a decoder circuit means responsive to said binary coded decimal outputs and generating said phase gate signals and said error gate signal; and said modulo counter means includes a two input NAND gate, a modulo counter, a set/reset modulo counter control, means connecting the set output of said modulo counter control to one input of said gate, means connecting said reference frequency to said other input of said gate, means connecting the output of said gate to the input of said modulo counter, and means connecting the output of said modulo counter to the reset input of said counter control.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-09 | 1976-10-09 | 1977-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-09 | 1980-10-09 | 1981-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-09 | 1984-10-09 | 1985-04-10 | $7700.00 | Window Closed / Lapsed |