Patent US3725791A successfully refreshed from Google Patents.
US3725791A
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US
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Divider circuits
Assignee: Societe Europeenne de Semi Conducteurs de Microelectronique SA SESCOSEM
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Filing: 1971-08-13
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Granted: 1973-04-03
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Expires: 1991-08-13
Abstract
Abstract A divider circuit, comprising an n-stage shift register having a feedback loop for maximum periodicity, is provided. A NOR operator has n-1 inputs connected with the first n-1 steps of said register and one output, constituting the single output of said divider circuit, loop-connected on to the divider input through an OR operator having a first and a second input, said first input being connected with said divider output and said second input being connected with the output of an ''''exclusive OR'''' operator having two inputs respectively connected with two predetermined steps of said register. The division ratio is 2n or 2n-1 according as said OR operator is exclusive or nonexclusive.
Inventors
- 👤 J Moreau
- 👤 J Boudry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:19
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; G; G04; G04G; G04G3/00; G04G3/02; G04G3/022; G04G3/025
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
213 words
A frequency divider for delivering a frequency which is a submultiple of a predetermined frequency comprising a shift register having a first and a second feed back loop and n stages respectively numbered (1,2, . . . n), a first input connected to said stage numbered (1), said stages having respective first inputs and outputs said output of each stage being connected to said first input of the adjacent stage, and respective second inputs for receiving synchronization pulses at said predetermined frequency, said first feed back loop comprising an exclusive OR operator, having two inputs respectively connected to said outputs of stages respectively numbered (i) and (k), with 1<i< k< n; and (i) and (k) being predetermined for a maximum periodicity for the register, and an output, said first feed back loop comprising a logic operator having an output connected to said input of said stage numbered (1), and having a third and a fourth inputs, said third input being connected to said output of said exclusive OR operator ; said second feed back loop comprising a NOR operator having N-1 inputs respectively connected to said outputs of said stages numbered (1 . . . n-1), and an output, feeding pulses at said submultiple frequency, said output being connected to said fourth input.
Claim 2
Dependent Claim
213 words
A frequency divider for delivering a frequency which is a submultiple of a predetermined frequency comprising a shift register having a first and a second feed back loop and n stages respectively numbered (1,2, . . . n), a first input connected to said stage numbered (1), said stages having respective first inputs and outputs said output of each stage being connected to said first input of the adjacent stage, and respective second inputs for receiving synchronization pulses at said predetermined frequency, said first feed back loop comprising an exclusive OR operator, having two inputs respectively connected to said outputs of stages respectively numbered (i) and (k), with 1<i< k< n; and (i) and (k) being predetermined for a maximum periodicity for the register, and an output, said first feed back loop comprising a logic operator having an output connected to said input of said stage numbered (1), and having a third and a fourth inputs, said third input being connected to said output of said exclusive OR operator ; said second feed back loop comprising a NOR operator having N-1 inputs respectively connected to said outputs of said stages numbered (1 . . . n-1), and an output, feeding pulses at said submultiple frequency, said output being connected to said fourth input.
Claim 3
Dependent Claim
16 words
A register as claimed in claim 1, wherein said logic operator is an exclusive OR operator.
Claim 4
Dependent Claim
14 words
A register as claimed in claim 1, wherein said operator is an OR operator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |