US3725573A
Expired / Lapsed
US
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Video buffer
Assignee: Lockheed Martin Corp
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Filing: 1971-08-31
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Granted: 1973-04-03
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Expires: 1991-08-31
Abstract
Abstract An image transmission system. A television camera scans a projected image and generates a video signal. An input circuit converts the video signal into a two-level signal which is sampled and stored digitally on a magnetic disk or drum. After the signals are stored, they are used to reconstruct a video signal by being recombined and combined with blanking, horizontal drive and synchronization signals from the television camera. All timing is controlled by signals recorded on timing tracks on the magnetic disk or drum.
Inventors
- 👤 A Wachtel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:18
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/78; H04N5/781
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
130 words
A system for displaying a recorded image on a display unit, said system comprising: A. a camera for generating control and electrical image signals representing the image, B. a converter energized by image signals for generating sequential sets of parallel digital signals in response thereto, C. a memory unit with means for 1. writing the parallel digital signal sets into given locations, and 2. generating master timing pulses, and 3. reading means generating output signals representing the stored signal sets in parallel, D. a synthesizer responsive to the memory output signals and control signals from said camera for energizing the display unit, and E. a timing circuit responsive to the master timing pulses from the memory unit for deriving therefrom timing signals for said camera, said converter and said synthesizer.
Claim 2
Independent Claim
130 words
A system for displaying a recorded image on a display unit, said system comprising: A. a camera for generating control and electrical image signals representing the image, B. a converter energized by image signals for generating sequential sets of parallel digital signals in response thereto, C. a memory unit with means for 1. writing the parallel digital signal sets into given locations, and 2. generating master timing pulses, and 3. reading means generating output signals representing the stored signal sets in parallel, D. a synthesizer responsive to the memory output signals and control signals from said camera for energizing the display unit, and E. a timing circuit responsive to the master timing pulses from the memory unit for deriving therefrom timing signals for said camera, said converter and said synthesizer.
Claim 3
Dependent Claim
5 words
generating master timing pulses, and
Claim 4
Dependent Claim
5 words
generating master timing pulses, and
Claim 5
Dependent Claim
52 words
A system as recited in claim 1 wherein said camera generates horizontal drive, blanking and synchronizing signals in response to the timing pulses from said timing circuit, said system additionally comprising means for coupling the horizontal drive, blanking and synchronizing signals to said synthesizer to thereby synchronize said synthesizer and said camera.
Claim 6
Dependent Claim
35 words
a second shift register for receiving the outputs from said conditioning unit in parallel in response to fourth control timing signals and serially shifting output pulses therefrom in response to fifth control timing signals, and
Claim 7
Dependent Claim
35 words
a second shift register for receiving the outputs from said conditioning unit in parallel in response to fourth control timing signals and serially shifting output pulses therefrom in response to fifth control timing signals, and
Claim 8
Dependent Claim
25 words
a multi-stage shift register unit for sampling the output from said converter and shifting the sampled information in response to second control timing signals, and
Claim 9
Dependent Claim
25 words
a multi-stage shift register unit for sampling the output from said converter and shifting the sampled information in response to second control timing signals, and
Claim 10
Dependent Claim
51 words
a multi-stage register unit for receiving the contents of said shift register unit in parallel in response to third control timing signals, said memory unit writing means being connected to receive and record the output of said register unit in parallel, and E. an output circuit for each display unit including:
Claim 11
Dependent Claim
51 words
a multi-stage register unit for receiving the contents of said shift register unit in parallel in response to third control timing signals, said memory unit writing means being connected to receive and record the output of said register unit in parallel, and E. an output circuit for each display unit including:
Claim 12
Dependent Claim
39 words
a synthesizer for generating an output video signal in response to the serial output pulses from said second shift register and the video control signals from said camera for transfer to the display unit in response to signals therefrom.
Claim 13
Dependent Claim
39 words
a synthesizer for generating an output video signal in response to the serial output pulses from said second shift register and the video control signals from said camera for transfer to the display unit in response to signals therefrom.
Claim 14
Dependent Claim
60 words
reading means generating output signals representing the stored signal sets in parallel, D. a synthesizer responsive to the memory output signals and control signals from said camera for energizing the display unit, and E. a timing circuit responsive to the master timing pulses from the memory unit for deriving therefrom timing signals for said camera, said converter and said synthesizer.
Claim 15
Dependent Claim
60 words
reading means generating output signals representing the stored signal sets in parallel, D. a synthesizer responsive to the memory output signals and control signals from said camera for energizing the display unit, and E. a timing circuit responsive to the master timing pulses from the memory unit for deriving therefrom timing signals for said camera, said converter and said synthesizer.
Claim 16
Dependent Claim
108 words
A system as recited in claim 1 wherein said converter comprises: A. a threshold circuit responsive to signals from said camera for generating one of two signals, B. a multi-stage register energized by first gating pulses from said timing circuit for sampling the output of said threshold circuit and for storing a group of signals in sequence, and C. a register unit having a stage corresponding to each stage in said shift register and responsive to second gating pulses from said timing unit for energizing said direct access memory unit with a plurality of signal sequences in parallel which represent the electrical image signal from said television camera.
Claim 17
Dependent Claim
87 words
A system as recited in claim 1 wherein said synthesizer includes; A. means for reading the signal sequences stored in said given locations in said direct access memory unit simultaneously, B. a register energized by said reading means in parallel, C. means for causing the contents of said register unit to be shifted therefrom in series, and D. a synthesizer responsive to the serial output from said register and to the control signals from said camera for producing a signal comprising control signals and electrical image signals.
Claim 18
Dependent Claim
62 words
An image recording and display system as recited in claim 1 including a plurality of display units, said memory unit having a plurality of locations for storing parallel signal sets, one location being reserved for each display unit, said system additionally comprising commutator means for routing a set of parallel signals from said converter to the appropriate location in said memory unit.
Claim 19
Dependent Claim
66 words
A system as recited in claim 1 wherein said converter comprises an amplifier with positive feedback for operating at either a first or second saturated condition, and means responsive to electrical image signals from said camera for converting first of said signals to a value which causes a first level of saturation and second of said signals to a level which causes second level of saturation.
Claim 20
Independent Claim
95 words
A system for transmitting an image to one of several remote display units responsive to video signals comprising: A. a recirculating memory unit including reading and writing means, said memory unit having first, second and third timing signals recorded thereon, B. a frequency converter responsive to said third timing signals from said memory unit for generating a plurality of control timing signals, C. a camera for converting the image into a video signal, said camera generating video control signals in response to first control timing signals from said frequency converter, D. an input circuit including:
Claim 21
Independent Claim
95 words
A system for transmitting an image to one of several remote display units responsive to video signals comprising: A. a recirculating memory unit including reading and writing means, said memory unit having first, second and third timing signals recorded thereon, B. a frequency converter responsive to said third timing signals from said memory unit for generating a plurality of control timing signals, C. a camera for converting the image into a video signal, said camera generating video control signals in response to first control timing signals from said frequency converter, D. an input circuit including:
Claim 22
Dependent Claim
44 words
A system as recited in claim 7 additionally comprising a commutator circuit between said input circuit register unit and said storage unit for routing the output from said register unit to a particular area in said memory unit assigned to a specific display unit.
Claim 23
Dependent Claim
80 words
A system a recited in claim 7 wherein said memory unit comprises: A. a magnetic disk for storing the timing signals and parallel output signals from said input circuit, B. means for rotating said magnetic disk past said reading and writing means, C. a master oscillator for generating first and second reference signals, and D. servo means responsive to said first and second timing signals on said disk and the first and second reference signals for controlling said rotating means.
Claim 24
Dependent Claim
60 words
A system aS recited in claim 7 wherein each output circuit conditioning unit comprises: A. means responsive to parallel signals from said reading means greater than a first threshold value or less than a second threshold value for generating a first voltage level signal, said threshold means generating a second voltage level for other signal values from said reading means.
Claim 25
Dependent Claim
34 words
A system as recited in claim 7 wherein each output circuit shift register unit includes a number of stages exceeding the number of stages in said input circuit multi-stage shift register unit by one.
Claim 26
Dependent Claim
41 words
A system as recited in claim 7 wherein said synthesizer circuit includes means responsive to blanking, horizontal drive and synchronization signals from said camera and the output from said second shift register for generating the video signal for a display unit.
Claim 27
Dependent Claim
53 words
A system as recited in claim 7 wherein said input circuit converter comprises means for setting first and second threshold levels, said converter generating a first signal in response to video signals greater than the first threshold level and a second signal in response to video signals less than the second threshold level.
Claim 28
Dependent Claim
62 words
A system as recited in claim 13 wherein said converter comprises: A. an operational amplifier including positive feedback means and inverting and non-inverting inputs, said video signal being coupled to said inverting input, B. means for summing the first threshold and video signals at the inverting input, and C. means for summing the second threshold and feedback signals at the non-inverting input.
Claim 29
Dependent Claim
61 words
A system as recited in claim 7 wherein the video signal frequency exceeds the maximum recording frequency of said memory unit by less than n times, said input circuit shift register unit and said input stage register unit each including n stages and the frequency of said second control timing signal being n times that of the third timing control signal.
Claim 30
Dependent Claim
59 words
A system as recited in claim 15 wherein said output circuit shift register unit includes (n + 1) stages, the second through nth stages being directly connected to said output conditioning unit, said first stage being connected to only said second stage to receive signals shifted therefrom in response to the fifth control timing signals from said frequency converter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |