US3573799A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial to parallel converter
Assignee: Automatic Telephone and Electric Co Ltd
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Filing: 1968-10-10
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Granted: 1971-04-06
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Expires: 1988-10-10
Abstract
Abstract A serial to parallel converter for converting serially transmitted data into parallel form, comprises rows of toggles (TA, TB, TC- TD, TE, TF- TG, TH, TI) which are arranged to be controlled for storing in turn the serial data received from respective inputs (LZ, LY and LX). The data stored in parallel form in toggles (TA, TB and TC) from input (LZ) is moved to toggles (TD, TE and TF) and next to toggles (TG, TH and TI) as serial data is received sequentially from inputs (LY and LX).
Inventors
- 👤 James Walter Drinnan
- 👤 Roy Harold Mauger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 05:21
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; G; G11; G11C; G11C19/00; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
375 words
A shift register circuit arrangement for converting binary information on a plurality of input leads from a succession of serial data bytes to a succession of parallel data bytes, of n bits each, and including n rows and n columns of bistable devices, the bistable devices of each row are individually connected in series by first connecting paths each extending between the output path of a bistable device and the input path of the succeeding bistable device in the particular row and the bistable devices of each column are individually connected in series by second connecting paths each extending between the output path of a bistable device and the input path of the corresponding bistable device in the succeeding row, each of said first and second connecting paths including first and second gating devices respectively and control means are included arranged firstly to exclusively actuate all said first gating devices for the passage of a signal indicating the state of each bistable device to the succeeding bistable device and said control means is arranged secondly to exclusively actuate all said second gating devices for the passage of a signal indicating the state of each bistable device to the corresponding bistable device and each input lead is individually connected (i) by way of an additional first gating device to the input path of a particular one of the bistable devices of the first column of bistable devices and (ii) by way of an additional second gating device to the input path of a correspondingly numbered bistable device of the first row of bistable devices and the output paths of the nth row of bistable devices, except the last bistable device in that row, are connected to further second gating devices and the output paths of the nth column of bistable devices, except the last bistable device in that column, are connected to further first gating devices, the output paths from said first and second further gating devices together with the output paths from said excepted bistable device are used to provide output paths from said shift register circuits, said additional and further first gating devices and said additional and further second gating devices being controlled in like manner to said first and second gating devices respectively.
Claim 2
Dependent Claim
375 words
A shift register circuit arrangement for converting binary information on a plurality of input leads from a succession of serial data bytes to a succession of parallel data bytes, of n bits each, and including n rows and n columns of bistable devices, the bistable devices of each row are individually connected in series by first connecting paths each extending between the output path of a bistable device and the input path of the succeeding bistable device in the particular row and the bistable devices of each column are individually connected in series by second connecting paths each extending between the output path of a bistable device and the input path of the corresponding bistable device in the succeeding row, each of said first and second connecting paths including first and second gating devices respectively and control means are included arranged firstly to exclusively actuate all said first gating devices for the passage of a signal indicating the state of each bistable device to the succeeding bistable device and said control means is arranged secondly to exclusively actuate all said second gating devices for the passage of a signal indicating the state of each bistable device to the corresponding bistable device and each input lead is individually connected (i) by way of an additional first gating device to the input path of a particular one of the bistable devices of the first column of bistable devices and (ii) by way of an additional second gating device to the input path of a correspondingly numbered bistable device of the first row of bistable devices and the output paths of the nth row of bistable devices, except the last bistable device in that row, are connected to further second gating devices and the output paths of the nth column of bistable devices, except the last bistable device in that column, are connected to further first gating devices, the output paths from said first and second further gating devices together with the output paths from said excepted bistable device are used to provide output paths from said shift register circuits, said additional and further first gating devices and said additional and further second gating devices being controlled in like manner to said first and second gating devices respectively.
Claim 3
Dependent Claim
87 words
A shift register circuit arrangement as claimed in claim 1 in which bistable devices are controlled by clock pulses produced by said control means which also includes a bistable circuit arranged to produce (i) a first selection signal, to activate all said first gating devices and all said first additional and first further gating devices when in one state and (ii) a second selecting signal, to activate all said second gating devices and all said second additional and second further gating devices, when in the other state.
Claim 4
Dependent Claim
146 words
A shift register circuit arrangement as claimed in claim 2 in which said bistable circuit is controlled by conditions derived from two clock pulses leads, each lead carrying a pulse pattern consisting of a train of n pulses followed by an equivalent period of no pulses and the pulse pattern on each clock pulse lead are arranged such that the train of n pulses on one lead corresponds with the no pulse period on the other clock pulse lead, one of said conditions being generated while the train of pulses are present on one of said clock pulse leads and being active to drive said bistable circuit to said one state, and the other of said conditions being generated while the train of pulses is present on the other of said clock pulse leads and being active to drive said bistable circuit to said other state.
Claim 5
Dependent Claim
374 words
A shift register circuit arrangement for converting binary information on a plurality of input leads from a succession of parallel data bytes to a succession of serial data bytes, of n bits each, and including n rows and n columns of bistable devices, the bistable devices of each row are individually connected in series by first connecting paths each extending between the output path of a bistable device and the input path of the succeeding bistable device in the particular row and the bistable devices of each column are individually connected in series by second connecting paths each extending between the output path of a bistable device and the input path of the corresponding bistable device in the succeeding row, each of said first and second connecting paths including first and second gating devices respectively and control means are included arranged firstly to exclusively actuate all said first gating devices for the passage of a signal indicating the state of each bistable device to the succeeding bistable device and said control means is arranged secondly to exclusively actuate all said second gating devices for the passage of a signal indicating the state of each bistable device to the corresponding bistable device and each input lead is individually connected (i) by way of an additional first gating device to the input path of a particular one of the bistable devices of the first column of bistable devices and (ii) by way of an additional second gating device to the input path of a correspondingly numbered bistable device of the first row of bistable devices and the output paths of the nth row of bistable devices, except the last bistable device in that row, are connected to further second gating devices and the output paths of nth row of bistable devices, except the last bistable device in that column, are connected to further first gating devices, the output paths from said first and second further gating devices together with the output paths from said excepted bistable device are used to provide output paths from said shift register circuits, said additional and further first gating devices and said additional and further second gating devices being controlled in like manner to said first and second gating devices respectively.
Claim 6
Dependent Claim
374 words
A shift register circuit arrangement for converting binary information on a plurality of input leads from a succession of parallel data bytes to a succession of serial data bytes, of n bits each, and including n rows and n columns of bistable devices, the bistable devices of each row are individually connected in series by first connecting paths each extending between the output path of a bistable device and the input path of the succeeding bistable device in the particular row and the bistable devices of each column are individually connected in series by second connecting paths each extending between the output path of a bistable device and the input path of the corresponding bistable device in the succeeding row, each of said first and second connecting paths including first and second gating devices respectively and control means are included arranged firstly to exclusively actuate all said first gating devices for the passage of a signal indicating the state of each bistable device to the succeeding bistable device and said control means is arranged secondly to exclusively actuate all said second gating devices for the passage of a signal indicating the state of each bistable device to the corresponding bistable device and each input lead is individually connected (i) by way of an additional first gating device to the input path of a particular one of the bistable devices of the first column of bistable devices and (ii) by way of an additional second gating device to the input path of a correspondingly numbered bistable device of the first row of bistable devices and the output paths of the nth row of bistable devices, except the last bistable device in that row, are connected to further second gating devices and the output paths of nth row of bistable devices, except the last bistable device in that column, are connected to further first gating devices, the output paths from said first and second further gating devices together with the output paths from said excepted bistable device are used to provide output paths from said shift register circuits, said additional and further first gating devices and said additional and further second gating devices being controlled in like manner to said first and second gating devices respectively.
Claim 7
Dependent Claim
88 words
A shift register circuit arrangement as claimed in claim 4 in which said bistable devices are controlled by clock pulses produced by said control means which also includes a bistable circuit arranged to produce (i) a first selection signal, to activate all said first gating devices and all said first additional and first further gating devices when in one state and (ii) a second selecting signal, to activate all said second gating devices and all said second additional and second further gating devices, when in the other state.
Claim 8
Dependent Claim
146 words
A shift register circuit arrangement as cLaimed in claim 5 in which said bistable circuit is controlled by conditions derived from two clock pulses lead, each lead carrying a pulse pattern consisting of a train of n pulses followed by an equivalent period of no pulses and the pulse pattern on each clock pulse lead are arranged such that the train of n pulses on one lead corresponds with the no pulse period on the other clock pulse lead, one of said conditions being generated while the train of pulses are present on one of said clock pulse leads and being active to drive said bistable circuit to said one state, and the other of said conditions being generated while the train of pulses is present on the other of said clock pulse leads and being active to drive said bistable circuit to said other state.
References Cited (Backward Citations)
US3209330A
Cited
US3355732A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |