Patent US3723715A successfully refreshed from Google Patents.
US3723715A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast modulo threshold operator binary adder for multi-number additions
Assignee: International Business Machines Corp
•
Filing: 1971-08-25
•
Granted: 1973-03-27
•
Expires: 1991-08-25
Abstract
Abstract A fast adder for adding more than three words, the correspondingly weighted bits of which are applied to respective bit column adders. The column adders simultaneously produce respective sum and carry result bits of overlapping positional significance or weight. The maximum number of result bits having the same weight is determined by the quantity of words to be added at the same time (which establishes the number of bits in each bit column). In the disclosed embodiment, seven words are added at a given time and no more than three of the generated result bits have the same weight. In effect, the seven operand words are reduced to a subtotal of three result operand words in one computational cycle irrespective of the bit length of the words being added. The subtotal operands are reduced to a final sum by application to conventional carry save and carry lookahead adders. Equal weighted wire-ORing and matrix memory techniques are employed in the respective column adders to conserve required computational hardware and to facilitate large scale circuit integration.
Inventors
- 👤 T Chen
- 👤 I Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:01
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/509; G06F7/60; G06F7/607
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
211 words
A fast adder for multi-word additions comprising: a plurality of bit column adders equal in number to the number of bits in the operand words to be added, each said column adder receiving input signals representing equally weighted bits of (2q-1) words to be added, each said column adder producing output signals representing a sum bit and (q-1) carry bits constituting the total of the respectively received bits of said numbers to be added; each said column adder comprising AND gates responsive to said input signals and producing signal outputs, means for combining said signal outputs in accordance with the quantity of identically valued bits in the numbers represented by said signal outputs, signal outputs representing the same quantity of identically-valued bits being commonly combined, and an X-Y matrix of conductors receiving said commonly combined signal outputs and having actuatable switches at selected matrix intersections, said switches being actuated by said commonly combined signal outputs, said switches being located along diagonals of said matrix in a plurality of different patterns, each pattern repeating over a respective number of matrix diagonals; q word registers, and means for distributing with proper relative weight said sum bit and carry bit signals to said q word registers, respectively, q being an integer greater than 2.
Claim 2
Dependent Claim
211 words
A fast adder for multi-word additions comprising: a plurality of bit column adders equal in number to the number of bits in the operand words to be added, each said column adder receiving input signals representing equally weighted bits of (2q-1) words to be added, each said column adder producing output signals representing a sum bit and (q-1) carry bits constituting the total of the respectively received bits of said numbers to be added; each said column adder comprising AND gates responsive to said input signals and producing signal outputs, means for combining said signal outputs in accordance with the quantity of identically valued bits in the numbers represented by said signal outputs, signal outputs representing the same quantity of identically-valued bits being commonly combined, and an X-Y matrix of conductors receiving said commonly combined signal outputs and having actuatable switches at selected matrix intersections, said switches being actuated by said commonly combined signal outputs, said switches being located along diagonals of said matrix in a plurality of different patterns, each pattern repeating over a respective number of matrix diagonals; q word registers, and means for distributing with proper relative weight said sum bit and carry bit signals to said q word registers, respectively, q being an integer greater than 2.
Claim 3
Dependent Claim
62 words
The fast adder defined in claim 1 and further including a plurality of bit registers equal in number to said plurality of digit column adders, each register storing said signals representing respective equally weighted bits of said words to be added, said column adders being connected to the outputs of respective bit registers, said word registers comprising portions of said bit registers.
Claim 4
Dependent Claim
26 words
The fast adder defined in claim 1 wherein each said respective number of matrix diagonals is exponentially related to every other respective number of matrix diagonals.
Claim 5
Dependent Claim
30 words
The fast adder defined in claim 3 wherein each said respective number of matrix diagonals is related to every other respective number of matrix diagonals by a power of 2.
Claim 6
Dependent Claim
11 words
The fast adder defined in claim 4 wherein q equals 3.
Claim 7
Dependent Claim
62 words
The fast adder defined in claim 5 and further including a plurality of bit registers equal in number to said plurality of digit column adders each register storing said signals representing respective equally weighted bits of said words to be added, said column adders being connected to the outputs of respective bit registers, said word registers comprising portions of said bit registers.
Claim 8
Dependent Claim
136 words
A bit column adder receiving input signals representing respective bits to be added and producing output signals representing a sum bit and carry bits constituting the total of the received bits, said column adder comprising: AND gates responsive to said input signals and producing signal outputs, means for combining said signal outputs in accordance with the quantity of identically valued bits in the numbers represented by said signal outputs, signal outputs representing the same quantity of identically-valued bits being commonly combined, and an X-Y matrix of conductors receiving said commonly combined signal outputs and having actuatable switches at selected matrix intersections, said switches being actuated by said commonly combined signal outputs, said switches being located along diagonals of said matrix in a plurality of different patterns, each pattern repeating over a respective number of matrix diagonals.
Claim 9
Dependent Claim
136 words
A bit column adder receiving input signals representing respective bits to be added and producing output signals representing a sum bit and carry bits constituting the total of the received bits, said column adder comprising: AND gates responsive to said input signals and producing signal outputs, means for combining said signal outputs in accordance with the quantity of identically valued bits in the numbers represented by said signal outputs, signal outputs representing the same quantity of identically-valued bits being commonly combined, and an X-Y matrix of conductors receiving said commonly combined signal outputs and having actuatable switches at selected matrix intersections, said switches being actuated by said commonly combined signal outputs, said switches being located along diagonals of said matrix in a plurality of different patterns, each pattern repeating over a respective number of matrix diagonals.
Claim 10
Dependent Claim
120 words
Apparatus receiving input signals representing respective binary bits and producing an output signal in response to predetermined combinations of said binary bits, said apparatus comprising: AND gates responsive to said input signals and producing signal outputs, means for combining said signal outputs in accordance with the quantity of identically valued bits in the numbers represented by said signal outputs, signal outputs representing the same quantity of identically-valued bits being commonly combined, and an X-Y matrix of conductors receiving said commonly combined signal outputs and having actuatable switches at selected matrix intersections, said switches being actuated by said commonly combined signal outputs, said switches being located along diagonals of said matrix in a pattern repeating over a number of matrix diagonals.
Claim 11
Dependent Claim
120 words
Apparatus receiving input signals representing respective binary bits and producing an output signal in response to predetermined combinations of said binary bits, said apparatus comprising: AND gates responsive to said input signals and producing signal outputs, means for combining said signal outputs in accordance with the quantity of identically valued bits in the numbers represented by said signal outputs, signal outputs representing the same quantity of identically-valued bits being commonly combined, and an X-Y matrix of conductors receiving said commonly combined signal outputs and having actuatable switches at selected matrix intersections, said switches being actuated by said commonly combined signal outputs, said switches being located along diagonals of said matrix in a pattern repeating over a number of matrix diagonals.
References Cited (Backward Citations)
US3636334A
Cited
US3603776A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-26 | 1976-09-25 | 1977-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-26 | 1980-09-25 | 1981-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-26 | 1984-09-25 | 1985-03-27 | $7700.00 | Window Closed / Lapsed |