Patent US3716800A successfully refreshed from Google Patents.
US3716800A
Expired / Lapsed
US
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Sample and hold circuit
Assignee: Gordon Engineering Co
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Filing: 1971-01-06
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Granted: 1973-02-13
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Expires: 1991-01-06
Abstract
Abstract In a sample and hold circuit employing one operational amplifier connected in a high impedance voltage follower configuration, a first switch is connected to the input of the amplifier and second and third switches are connected serially between the output and input terminals of the amplifier. A capacitor is connected between the junction point of the second and third switch and ground. During the sample period, the first and third switches are energized to the ON state and the capacitor is charged to the voltage appearing at the output of the amplifier, the second switch being in the OFF state. During the hold period, the second switch is energized to the ON state and the charge on the capacitor is applied to the input of the amplifier, the first and third switches being in the OFF state.
Inventors
- 👤 Rocco J Di
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:00
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
261 words
A sample and hold circuit comprising: a. amplifier means having input and output terminals; b. first switch means electrically connected to the input terminal of said amplifier means; c. second switch means electrically connected to the output terminal of said amplifier means; d. third switch means electrically connected to the input terminal of said amplifier means and said second switch means; and e. first capacitor means connected between a ground and the junction of said second and third switch means; f. during the sample period, said first and second switch means are in an ON state and said third switch means is in an OFF state, said first capacitor means being charged by the signal appearing at the output terminal of said amplifier means; g. during the hold period, said third switch means is in the ON state and said first and second switch means are in the OFF state, the charge on said first capacitor means appearing at the input terminal of said amplifier means; h. said second and third switch means being a matched pair of field effect transistor means which operate to cancel transients applied to their respective gates during the switching operation from the sample period to the hold period; i. fourth switch means connected serially between the input terminal of said amplifier means and a ground; j. second capacitor means interposed between the outpuT terminal of said amplifier means and said second switch means; and k. fifth switch means connected serially between ground and the junction point of said second capacitor means and second switch means.
Claim 2
Dependent Claim
261 words
A sample and hold circuit comprising: a. amplifier means having input and output terminals; b. first switch means electrically connected to the input terminal of said amplifier means; c. second switch means electrically connected to the output terminal of said amplifier means; d. third switch means electrically connected to the input terminal of said amplifier means and said second switch means; and e. first capacitor means connected between a ground and the junction of said second and third switch means; f. during the sample period, said first and second switch means are in an ON state and said third switch means is in an OFF state, said first capacitor means being charged by the signal appearing at the output terminal of said amplifier means; g. during the hold period, said third switch means is in the ON state and said first and second switch means are in the OFF state, the charge on said first capacitor means appearing at the input terminal of said amplifier means; h. said second and third switch means being a matched pair of field effect transistor means which operate to cancel transients applied to their respective gates during the switching operation from the sample period to the hold period; i. fourth switch means connected serially between the input terminal of said amplifier means and a ground; j. second capacitor means interposed between the outpuT terminal of said amplifier means and said second switch means; and k. fifth switch means connected serially between ground and the junction point of said second capacitor means and second switch means.
Claim 3
Dependent Claim
261 words
A sample and hold circuit comprising: a. amplifier means having input and output terminals; b. first switch means electrically connected to the input terminal of said amplifier means; c. second switch means electrically connected to the output terminal of said amplifier means; d. third switch means electrically connected to the input terminal of said amplifier means and said second switch means; and e. first capacitor means connected between a ground and the junction of said second and third switch means; f. during the sample period, said first and second switch means are in an ON state and said third switch means is in an OFF state, said first capacitor means being charged by the signal appearing at the output terminal of said amplifier means; g. during the hold period, said third switch means is in the ON state and said first and second switch means are in the OFF state, the charge on said first capacitor means appearing at the input terminal of said amplifier means; h. said second and third switch means being a matched pair of field effect transistor means which operate to cancel transients applied to their respective gates during the switching operation from the sample period to the hold period; i. fourth switch means connected serially between the input terminal of said amplifier means and a ground; j. second capacitor means interposed between the outpuT terminal of said amplifier means and said second switch means; and k. fifth switch means connected serially between ground and the junction point of said second capacitor means and second switch means.
Claim 4
Dependent Claim
261 words
A sample and hold circuit comprising: a. amplifier means having input and output terminals; b. first switch means electrically connected to the input terminal of said amplifier means; c. second switch means electrically connected to the output terminal of said amplifier means; d. third switch means electrically connected to the input terminal of said amplifier means and said second switch means; and e. first capacitor means connected between a ground and the junction of said second and third switch means; f. during the sample period, said first and second switch means are in an ON state and said third switch means is in an OFF state, said first capacitor means being charged by the signal appearing at the output terminal of said amplifier means; g. during the hold period, said third switch means is in the ON state and said first and second switch means are in the OFF state, the charge on said first capacitor means appearing at the input terminal of said amplifier means; h. said second and third switch means being a matched pair of field effect transistor means which operate to cancel transients applied to their respective gates during the switching operation from the sample period to the hold period; i. fourth switch means connected serially between the input terminal of said amplifier means and a ground; j. second capacitor means interposed between the outpuT terminal of said amplifier means and said second switch means; and k. fifth switch means connected serially between ground and the junction point of said second capacitor means and second switch means.
Claim 5
Dependent Claim
28 words
The sample and hold circuit as claimed in claim 1 including means for selectively controlling the switching states of said first, second, third, fourth and fifth switch means.
Claim 6
Dependent Claim
20 words
The sample and hold circuit as claimed in claim 1 wherein said first switch means is field effect transistor means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-13 | 1976-08-14 | 1977-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-13 | 1980-08-14 | 1981-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-13 | 1984-08-14 | 1985-02-13 | $7700.00 | Window Closed / Lapsed |