Patent US3711693A successfully refreshed from Google Patents.
US3711693A
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Modular bcd and binary arithmetic and logical system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1971-06-30
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Granted: 1973-01-16
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Expires: 1991-06-30
Abstract
Abstract An arithmetic and logical unit for receiving four bit portions (quartets) of two input operands, a carry-in and several function control signals generates selectively several functions of the operands, including decimal and binary addition and subtraction functions or a desired logical function and provides carry lookahead and carry signals. A set of conversion gates selectively provides either a true or an excess-6 form of the first operand quartet while a complementation set of gates selectively provides a true or 1''s complement form of the second operand quartet. Bit pairs, from the corresponding positions in the resulting quartets, are combined to produce elementary logical functions, including the AND, inclusive OR and exclusive OR functions. In parallel, these elementary functions, an input carry bit, a set of carry look-ahead gates, a set of adder gates and a pair of control signals respectively provide carry signals and the selected function of the operands. A set of decimal correction gates, responsive to the carry signals, are used to correct the adder gate output for decimal addition and subtraction, when necessary.
Inventors
- 👤 J Dahl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:19
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/492; G06F7/493; G06F7/494; G06F7/50; G06F7/505; G06F7/506; G06F7/508; G06F7/57; G06F7/575; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3832; G06F2207/3836; G06F2207/492; G06F2207/4921
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
183 words
A function generator module comprising: A. a set of conversion gates, responsive to a first input quartet operand, for selectively adding the value six to said first operand; B. a set of elementary logical gates, responsive to the outputs of said set of conversion gates and a second input quartet of bits, for generating sets of functions, for respective bit pairs, each set of functions providing a complete logic set; C. logical gate means, responsive to the outputs of said set of elementary logical gates and a carry-in signal, for selectively generating the binary sum bits of the input operands and the carry-in or a selected logical function; D. a set of decimal correction gates, connected to said logical gate means for selectively adding ten modulo sixteen to said sum bits; E. a set of carry look-ahead gates, connected to said set of elementary logical gates, for generating a carry-out for said module; F. logic control means, responsive to input function selection signals, for selecting the desired logical gate means output, and for enabling said set of decimal correction gates for decimal arithmetic.
Claim 2
Dependent Claim
183 words
A function generator module comprising: A. a set of conversion gates, responsive to a first input quartet operand, for selectively adding the value six to said first operand; B. a set of elementary logical gates, responsive to the outputs of said set of conversion gates and a second input quartet of bits, for generating sets of functions, for respective bit pairs, each set of functions providing a complete logic set; C. logical gate means, responsive to the outputs of said set of elementary logical gates and a carry-in signal, for selectively generating the binary sum bits of the input operands and the carry-in or a selected logical function; D. a set of decimal correction gates, connected to said logical gate means for selectively adding ten modulo sixteen to said sum bits; E. a set of carry look-ahead gates, connected to said set of elementary logical gates, for generating a carry-out for said module; F. logic control means, responsive to input function selection signals, for selecting the desired logical gate means output, and for enabling said set of decimal correction gates for decimal arithmetic.
Claim 3
Dependent Claim
28 words
The function generator of claim 1 further comprising: G. logic in said set of carry look-ahead gates for generating carry propagate and generate signals for the function generator.
Claim 4
Dependent Claim
33 words
The function generator of claim 2 further comprising: H. a set of complement gates, responsive to said second input quartet of bits and said logic control means for selectively complementing said second input.
Claim 5
Dependent Claim
288 words
A function generator for performing signed binary and decimal arithmetic operations, together with basic logical operations on a pair of bit quartet operands comprising: A. conversion operand gating means, responsive to a first input bit quartet operand, for selectively generating four bit signals representing either the excess-6 coded representation or the true representation of a first input operand; B. first input control means responsive to input control signals representing binary/decimal and add/subtract functions and connected to said first operand gating means for selecting the excess-6 coded representation if and only if a decimal add operation is specified by the input control signals; C. complement operand gating means, responsive to a second input bit quartet operand, for selectively generating four bit signals representing either the second operand or its 1''s complement in accordance with input control signals specifying an add or subTract operation; D. logical gating means responsive to the outputs of said conversion and complement operand gating means for generating four sets of signals, each set being derived from a pair of input signals, one each from said respective operand gating means, said set including the inclusive OR and AND functions of each of said pair of input signals; E. carry gating means responsive to the outputs of said logical gating means for generating a carry-out signal; F. adder means responsive to the outputs of said logical gating means and a carry-in to the function generator for selectively generating the binary sum of or a logical function of the outputs of said first and second operand gating means, in accordance with the input control signals; G. decimal correction means connected to said adder means for correcting the adder output in response to said carry-out signal representing no carry.
Claim 6
Dependent Claim
288 words
A function generator for performing signed binary and decimal arithmetic operations, together with basic logical operations on a pair of bit quartet operands comprising: A. conversion operand gating means, responsive to a first input bit quartet operand, for selectively generating four bit signals representing either the excess-6 coded representation or the true representation of a first input operand; B. first input control means responsive to input control signals representing binary/decimal and add/subtract functions and connected to said first operand gating means for selecting the excess-6 coded representation if and only if a decimal add operation is specified by the input control signals; C. complement operand gating means, responsive to a second input bit quartet operand, for selectively generating four bit signals representing either the second operand or its 1''s complement in accordance with input control signals specifying an add or subTract operation; D. logical gating means responsive to the outputs of said conversion and complement operand gating means for generating four sets of signals, each set being derived from a pair of input signals, one each from said respective operand gating means, said set including the inclusive OR and AND functions of each of said pair of input signals; E. carry gating means responsive to the outputs of said logical gating means for generating a carry-out signal; F. adder means responsive to the outputs of said logical gating means and a carry-in to the function generator for selectively generating the binary sum of or a logical function of the outputs of said first and second operand gating means, in accordance with the input control signals; G. decimal correction means connected to said adder means for correcting the adder output in response to said carry-out signal representing no carry.
Claim 7
Dependent Claim
59 words
The function generator of claim 4 further comprising: H. first level logic in said logical gating means for generating the AND and OR functions of respective bit pairs of said input operands; I. logic in said carry gating means, responsive to the outputs of said first level logic, for generating carry propagate and generate signals for the function generator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-16 | 1976-07-17 | 1977-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-16 | 1980-07-17 | 1981-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-16 | 1984-07-17 | 1985-01-16 | $7700.00 | Window Closed / Lapsed |