Patent US3708699A successfully refreshed from Google Patents.
US3708699A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed analog switching with fet
Assignee: International Business Machines Corp
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Filing: 1971-06-21
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Granted: 1973-01-02
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Expires: 1991-06-21
Abstract
Abstract A field-effect transistor is inserted in the series feedback path of a bipolar transistor at whose base terminal the analog input signal to be sampled is applied. The bipolar transistor is continuously maintained in its conductive state by drawing a current I0 from the emitter. The field-effect transistor is switched back and forth between its high and low impedance states by a sampling signal applied to its gate. The analog input signal is amplified, and therefore sampled, only when the field-effect transistor is in its low impedance state. An N-channel sampler-multiplexer is obtained by seriesconnecting a number of the above-described switches in a chain, with the gate electrodes of the field-effect transistors of all of the stages being connected to a common sampling line, and with the collector electrodes of all of the bipolar transistors of all of the stages delivering their sampled output signals into a common output line. To clearly separate the individual output signals, delay sections are inserted in the output line between neighboring stages.
Inventors
- 👤 A Frei
- 👤 P Vettiger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:21
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H03F; H03F3/00; H03F3/72; H03G; H03G1/00; H03G1/0005; H03G1/0088; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
199 words
A sampling circuit for sampling an analog input signal in response to a sampling signal comprising: transistor amplifier means coupled in common emitter configuration and arranged to amplify said analog input signal in accordance with the magnitude of the series impedance in the emitter circuit thereof; current source means coupled to said emitter to continuously draw a fixed current therefrom; field effect transistor means having a source, drain and gate electrode with the drain-source variable impedance path thereof coupled in series in said emitter circuit and with said gate electrode coupled to said sampling signal so as to vary said impedance in accordance with said sampling signal, said sampling signal acting to switch said field effect transistor means between a low conduction state and high conduction state so as to thereby vary the series impedance in said emitter circuit so as to increase the gain of said transistor amplifier means from a level insufficient to provide any appreciable output signal to a level sufficient to provide an appreciable output signal representation of a sample of said analog input signal; and capacitor means coupled between said gate electrode and the base electrode of the transistor of said transistor amplifier means.
Claim 2
Dependent Claim
199 words
A sampling circuit for sampling an analog input signal in response to a sampling signal comprising: transistor amplifier means coupled in common emitter configuration and arranged to amplify said analog input signal in accordance with the magnitude of the series impedance in the emitter circuit thereof; current source means coupled to said emitter to continuously draw a fixed current therefrom; field effect transistor means having a source, drain and gate electrode with the drain-source variable impedance path thereof coupled in series in said emitter circuit and with said gate electrode coupled to said sampling signal so as to vary said impedance in accordance with said sampling signal, said sampling signal acting to switch said field effect transistor means between a low conduction state and high conduction state so as to thereby vary the series impedance in said emitter circuit so as to increase the gain of said transistor amplifier means from a level insufficient to provide any appreciable output signal to a level sufficient to provide an appreciable output signal representation of a sample of said analog input signal; and capacitor means coupled between said gate electrode and the base electrode of the transistor of said transistor amplifier means.
Claim 3
Dependent Claim
16 words
The sampling circuit as set forth in claim 1 wherein said transistor is a bipolar transistor.
Claim 4
Dependent Claim
173 words
A sampling circuit for sampling an analog input signal in accordaNce with a sampling signal, comprising: bipolar transistor means having an emitter, base and collector and connected in common emitter circuit configuration as an amplifier for amplifying said input signal coupled to said base, means for continuously causing a fixed current to flow in said emitter; field effect transistor means having a source, drain and gate electrode with the source-drain path arranged in the emitter circuit of said bipolar transistor means as a controllable resistance in series with said emitter and with said gate electrode coupled to said sampling signal, said sampling signal comprising pulses which switch said field effect transistor means from a high impedance state where the gain of said bipolar transistor means is zero to a low impedance state where the gain of said bipolar transistor means changes to a fixed value and said input signal is sampled; and capacitor means coupled between the base of said bipolar transistor means and the gate electrode of said field effect transistor means.
Claim 5
Dependent Claim
173 words
A sampling circuit for sampling an analog input signal in accordaNce with a sampling signal, comprising: bipolar transistor means having an emitter, base and collector and connected in common emitter circuit configuration as an amplifier for amplifying said input signal coupled to said base, means for continuously causing a fixed current to flow in said emitter; field effect transistor means having a source, drain and gate electrode with the source-drain path arranged in the emitter circuit of said bipolar transistor means as a controllable resistance in series with said emitter and with said gate electrode coupled to said sampling signal, said sampling signal comprising pulses which switch said field effect transistor means from a high impedance state where the gain of said bipolar transistor means is zero to a low impedance state where the gain of said bipolar transistor means changes to a fixed value and said input signal is sampled; and capacitor means coupled between the base of said bipolar transistor means and the gate electrode of said field effect transistor means.
Claim 6
Dependent Claim
33 words
The sampling circuit as set forth in claim 3 wherein said means for continuously causing a current to flow comprises a current source coupled to said emitter for drawing a fixed current therefrom.
Claim 7
Dependent Claim
61 words
The sampling circuit as set forth in claim 4 wherein said current source comprises further transistor means arranged so that the base electrode thereof is held at a quiescent voltage level by voltage divider circuit means with said voltage divider circuit means including a diode arranged to compensate for variations in current in said further transistor, caused by variations in temperature.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-02 | 1976-07-03 | 1977-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-02 | 1980-07-03 | 1981-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-02 | 1984-07-03 | 1985-01-02 | $7700.00 | Window Closed / Lapsed |