Signal translating stage

Claim 2

A signal translating stage comprising: a pair of semiconductor amplifier devices, each having first, second and third electrodes; input circuit means coupled to the third electrode of one of said devices for supplying signals to be translated by said stage; output circuit means coupled to the third electrode of the other of said devices for deriving translated signals corresponding to said supplied signals; means for direct current coupling said third electrode of said one device to said second electrode of said other device means, including a direct cUrrent impedance, for coupling said second electrode of said one device to said second electrode of said other device and for coupling said first electrodes of said devices in common; and control means coupled to the second electrode of said one of said devices for supplying direct current voltages thereto to vary the transconductance of said other device without substantial variation of transconductance of said one device and thereby vary the amplitude of said derived translated signals.

Claim 3

A signal translating stage as defined in claim 1 wherein said semiconductor amplifier devices comprise a pair of transistors disposed in a single integrated circuit, and wherein said first, second and third electrodes correspond to the emitter, base and collector electrodes of said transistors, respectively.

Claim 4

A signal translating stage as defined in claim 2 wherein said input circuit means includes a first resistor coupling a source of signals to be translated to the collector electrode of said one semiconductor amplifier transistor device and wherein said output circuit means includes a second resistor coupling a source of energizing potential to the collector electrode of said other semiconductor amplifier transistor device.

Claim 5

A signal translating stage as defined in claim 3 wherein said means including a direct impedance includes direct current connections between the emitter electrodes of said semiconductor amplifier transistor devices, a direct current connection between the collector electrode of said one and the base electrode of said other semiconductor amplifier device, and a third resistor connected between the collector and base electrodes of said one semiconductor amplifier transistor device.

Claim 6

A signal translating stage as defined in claim 4 wherein said control means includes a source of controllable direct current voltage and a fourth resistor connecting the base electrode of said one semiconductor amplifier transistor device to said direct current voltage source.

Claim 7

A signal translating stage as defined in claim 5 wherein the resistance value of said fourth resistor is substantially greater than the resistance value of said third resistor and wherein the input impedance at the base electrode of said one semiconductor amplifier transistor device exceeds the resistance value of said third resistor.

Claim 8

A signal translating stage as defined in claim 1 wherein: said direct current impedance comprises a first resistor having a resistance value less than the input impedance at the second electrode of said one device.

Claim 9

A signal translating stage as defined in claim 7 wherein: said control means comprises a source of direct voltage and a second resistor coupled to said second electrode of said one device, and the resistance value of said first resistor is substantially less than the resistance values of said second resistor and said input impedance.

Claim 10

A signal translating stage comprising: first, second and third terminals; first, second and third transistors, each having emitter, base and collector electrodes; first and second direct connections from the emitter electrodes of said first and second transistors to said first terminal; a direct connection from the collector electrode of said third transistor to said second terminal; a direct connection from the collector electrode of said first transistor to the base electrode of said second transistor; a first resistor connected between the collector electrode of said first transistor and the emitter electrode of said third transistor; a second resistor connected between the collector electrode of said second transistor and said second terminal; a third resistor connected between the collector and base electrodes of said first transistor; a fourth resistor connected between the base electrode of said first transistor and said third terminal; input circuit means coupled to the base electrode of said third transisTor for supplying signals to be translated by said stage; output circuit means coupled to the collector electrode of said second transistor for deriving translated signals corresponding to said supplied signals; and control means coupled to said third terminal for supplying controllable direct current voltages to vary the bias on said first transistor to control the amplitude of said derived translated signals.

Claim 11

A signal translating stage comprising: first, second and third terminals; first, second and third transistors, each having emitter, base and collector electrodes; first and second direct connections from the emitter electrodes of said first and second transistors to said first terminal; a direct connection from the collector electrode of said third transistor to said second terminal; a direct connection from the collector electrode of said first transistor to the base electrode of said second transistor; a first resistor connected between the collector electrode of said first transistor and the emitter electrode of said third transistor; a second resistor connected between the collector electrode of said second transistor and said second terminal; a third resistor connected between the collector and base electrodes of said first transistor; a fourth resistor connected between the base electrode of said first transistor and said third terminal; input circuit means coupled to the base electrode of said third transisTor for supplying signals to be translated by said stage; output circuit means coupled to the collector electrode of said second transistor for deriving translated signals corresponding to said supplied signals; and control means coupled to said third terminal for supplying controllable direct current voltages to vary the bias on said first transistor to control the amplitude of said derived translated signals.