A digital memory shift register incorporating target data averaging through a digital smoothing loop

Claim 1

A digital memory shift register for storage of a multitude of target signal digital words with provision for constantly updating these target signal digital words and for smoothing the digital words for display and analysis comprising: a plurality of shift register modules coupled together to produce a long serial memory shift register having a single input and an output; a full serial adder having a first input adapted to receive a new target digital word, a second input, and an output and a full serial subtractor having a first input coupled to said full serial adder output, and a second input, and an output coupled to said plurality of shift register modules single input; a supplemental shift register of 32 bits coupled to said memory shift register output with an output for the leAst significant bit, a plurality of other parallel outputs, and an output of the most significant bit of the target information taken therefrom; a multiplexer circuit having a plurality of inputs coupled to receive said plurality of other parallel outputs on said inputs and having a three-line digital word control select inputs for dividing the digital word in said supplemental register applied by said parallel outputs to produce a divided digital word on an output; a logic system of NAND gates, the output of said least significant bit being through first and second NAND gates to said full adder second input to add in old target signal information with new target digital signal information therein by way of said first input to update this target information, the output of said multiplexer being through third and fourth NAND gates to said full subtractor by said second input to leave only the significant part of said target digital word established by said three-line digital control word, and the most significant bit output being coupled through fifth, sixth, seventh, and said fourth NAND gates to said full subtractor second input to establish the sign of the multiplexer digital word, said first, third, and fifth, NAND gates having fault signals applied thereto as second inputs; and a timing source coupled to said plurality of shift register modules, to said supplemental register, to said full adder, and to said full subtractor to synchronize the counting sequence and the circulating and updating of said digital target signal information whereby the target signal digital information is memorized and smoothed for steady flow of this digital information to the display and analysis sections of a sonar receiver.