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US3703709A
Expired / Lapsed
US
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High speed associative memory circuits
Assignee: NEC Corp
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Filing: 1970-05-21
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Granted: 1972-11-21
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Expires: 1990-05-21
Abstract
Abstract A high-speed associative memory circuit is disclosed comprising a flip-flop operating as a memory storage circuit, and a pair of switching transistors connected to the ''''true'''' and ''''not'''' output terminals of the flip-flop. The latter transistor pair thus defines a circuit for detecting the state of the flip-flop transistors.
Inventors
- 👤 Shigeki Matsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:17
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
145 words
An associative memory circuit comprising a flip-flop circuit containing a pair of cross-connected transistors, first and second bipolar switching transistors each having a base, an emitter, and a collector terminal, said base terminals being connected respectively to the ''''true'''' and ''''not'''' terminals of said flip-flop circuit, means comprising first and second impedance elements and first and second data signal terminals for applying data signals to said emitter electrodes of said first and second switching transistors through said first and second impedance elements, respectively, means comprising a word select terminal for applying a word select signal to both of said collector terminals of said first and second switching transistors, and clamping means comprising first and second diode means respectively coupled between the collectors and bases of said first and second switching transistors for preventing saturation of the associated one of said first and second switching transistors.
Claim 2
Dependent Claim
145 words
An associative memory circuit comprising a flip-flop circuit containing a pair of cross-connected transistors, first and second bipolar switching transistors each having a base, an emitter, and a collector terminal, said base terminals being connected respectively to the ''''true'''' and ''''not'''' terminals of said flip-flop circuit, means comprising first and second impedance elements and first and second data signal terminals for applying data signals to said emitter electrodes of said first and second switching transistors through said first and second impedance elements, respectively, means comprising a word select terminal for applying a word select signal to both of said collector terminals of said first and second switching transistors, and clamping means comprising first and second diode means respectively coupled between the collectors and bases of said first and second switching transistors for preventing saturation of the associated one of said first and second switching transistors.
Claim 3
Dependent Claim
145 words
An associative memory circuit comprising a flip-flop circuit containing a pair of cross-connected transistors, first and second bipolar switching transistors each having a base, an emitter, and a collector terminal, said base terminals being connected respectively to the ''''true'''' and ''''not'''' terminals of said flip-flop circuit, means comprising first and second impedance elements and first and second data signal terminals for applying data signals to said emitter electrodes of said first and second switching transistors through said first and second impedance elements, respectively, means comprising a word select terminal for applying a word select signal to both of said collector terminals of said first and second switching transistors, and clamping means comprising first and second diode means respectively coupled between the collectors and bases of said first and second switching transistors for preventing saturation of the associated one of said first and second switching transistors.
Claim 4
Dependent Claim
145 words
An associative memory circuit comprising a flip-flop circuit containing a pair of cross-connected transistors, first and second bipolar switching transistors each having a base, an emitter, and a collector terminal, said base terminals being connected respectively to the ''''true'''' and ''''not'''' terminals of said flip-flop circuit, means comprising first and second impedance elements and first and second data signal terminals for applying data signals to said emitter electrodes of said first and second switching transistors through said first and second impedance elements, respectively, means comprising a word select terminal for applying a word select signal to both of said collector terminals of said first and second switching transistors, and clamping means comprising first and second diode means respectively coupled between the collectors and bases of said first and second switching transistors for preventing saturation of the associated one of said first and second switching transistors.
Claim 5
Dependent Claim
18 words
The memory circuit of claim 1, in which said first and second diode means comprise Schottky barrier diodes.
Claim 6
Dependent Claim
177 words
An associative memory circuit comprising a flip-flop circuit including a pair of cross-connected transistors, first and second bipolar switching transistors each having a base, and emitter, and a collector terminal, said base terminals being connected respectively to the ''''true'''' or ''''not'''' terminals of said flip flop circuit, means for applying data signals to said emitters of said first and second switching transistors, means for applying a word select signal to said collectors of said first and second switching transistors, said word select signal applying means comprising a word select terminal coupled in common to said collectors and first and second impedance elements, said data signal applying means comprising first and second data signal terminals respectively coupled to said emitters through said first and second impedance elements, third and fourth transistors respectively coupled to said data signal terminals, a fifth transistor coupled to said word select terminal, and means for applying a complementary data signal to said third and fourth transistors and for applying a write command signal to said word select terminal during a data write-in operation.
Claim 7
Dependent Claim
177 words
An associative memory circuit comprising a flip-flop circuit including a pair of cross-connected transistors, first and second bipolar switching transistors each having a base, and emitter, and a collector terminal, said base terminals being connected respectively to the ''''true'''' or ''''not'''' terminals of said flip flop circuit, means for applying data signals to said emitters of said first and second switching transistors, means for applying a word select signal to said collectors of said first and second switching transistors, said word select signal applying means comprising a word select terminal coupled in common to said collectors and first and second impedance elements, said data signal applying means comprising first and second data signal terminals respectively coupled to said emitters through said first and second impedance elements, third and fourth transistors respectively coupled to said data signal terminals, a fifth transistor coupled to said word select terminal, and means for applying a complementary data signal to said third and fourth transistors and for applying a write command signal to said word select terminal during a data write-in operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-11-21 | 1976-05-22 | 1976-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-11-21 | 1980-05-22 | 1980-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-11-21 | 1984-05-22 | 1984-11-21 | $7700.00 | Window Closed / Lapsed |