Pulse-width modulated dc to dc converter with zero percent duty cycle capability

Claim 2

A DC to DC converter comprising a pair of switching devices, means to compare the output signal of said converter with a reference signal, pulse signal means to control said switching devices including means to modulate said pulse signals comprising a periodic pulse source, a first means to generate a fixed duration pulse triggered by said periodic pulse source, a second means triggered by said periodic pulse source to generate a pulse whose duration is variable in response to said means to compare, means to couple the output of said second means to generate to said switching devices and means to inhibit the output of said sEcond means to generate during the interval and responsive to the pulse output of said first means to generate.

Claim 3

A DC to DC converter as defined in claim 1 wherein the outputs of said first and second means to generate are applied to a NOR gate, the output of said NOR gate being coupled in parallel to two AND gates and said AND gates alternately enabled in response to the complementary outputs of a flip-flop responsive to said periodic pulse source.

Claim 4

A DC to DC converter as defined in claim 2 wherein said second means to generate includes a variable timing circuit with a controlled impedance charging path, a soft start connected across said controlled impedance charging path to limit the converter output upon initial energization, said soft start circuit comprising a transistor and a charging resistor connected in series and shunting said controlled impedance, a charging capacitor connected to the base of said transistor whereby the charge current drawn by said capacitor upon initial energization of said converter saturates said transistor and limits the pulse duration of the output of said second means to generate to limit the output signal of said converter.

Claim 5

A DC to DC converter as defined in claim 1 wherein said first means to generate comprises a first monostable multivibrator with a first and second complementary output and said second means to generate comprises a second monostable multivibrator with a variable timing circuit and having first and second complementary outputs phase related to the complementary output of said first monostable multivibrator, first and second AND gates, flip-flop means responsive to said periodic pulse source to alternately enable said first and second AND gates, and the first complementary output of said first multivibrator and the second complementary output of said second multivibrator, each being connected in parallel to said first and second AND gates.

Claim 6

A DC to DC converter as defined in claim 4 wherein said variable timing circuit includes a controlled impedance charging path, a soft start circuit connected across said controlled impedances of said variable timing circuit to limit the converter output upon initial energization, said soft start circuit comprising a transistor and a charging resistor connected in series and shunting said controlled impedance, a charging capacitor connected to the base of said transistor whereby the charge current drawn by said capacitor upon initial energization of said converter saturates said transistor and limits the pulse duration of the output of said second monostable multivibrator to limit the output signal of said converter.

Claim 7

A DC to DC converter comprising, an inverter circuit including two oppositely phased switching devices, output means coupled to said inverter circuit, means to monitor the signal output of said output means including means to generate an error signal should the signal magnitude depart from some designated value, switching control means coupled to drive said switching devices and responsive to said error signal, said switching control means including a repetitive pulse source, means to modulate the pulse width output of said pulse source in response to said error signal and means to inhibit for a fixed time period at the start of each cycle the transmission of an initial portion of said modulated pulse output and means to alternately steer said modulated pulses to said oppositely phased switching devices, wherein said switching devices operate at a zero percent duty cycle if said modulated pulse terminates within the duration of said fixed time period.

Claim 8

A DC to DC converter comprising, an inverter circuit including two oppositely phased switching devices, output means coupled to said inverter circuit, means to monitor the signal output of said output means including means to generate an error signal should the signal magnitude depart from some designated value, switching control means coupled to drive said switching devices and responsive to said error signal, said switching control means including a repetitive pulse source, means to modulate the pulse width output of said pulse source in response to said error signal and means to inhibit for a fixed time period at the start of each cycle the transmission of an initial portion of said modulated pulse output and means to alternately steer said modulated pulses to said oppositely phased switching devices, wherein said switching devices operate at a zero percent duty cycle if said modulated pulse terminates within the duration of said fixed time period.

Claim 9

A DC to DC converter as defined in claim 6 wherein said means to modulate comprises a pulse circuit with a variable timing arrangement responsive to said error signal and said means to inhibit comprises a second pulse circuit with a fixed timing arrangement, means to utilize the signal output of said second pulse circuit to block transmission of the output of said first pulse circuit.

Claim 10

A DC to DC converter as defined in claim 7 further including means to limit modulation of the pulse output of said pulse source at the initial energization of said converter including a current path comprising a transistor, means to bias said transistor into saturation, an energy storage device coupled to said transistor and means to store energy in said storage device and turn said transistor off upon the attainment of a certain energy level.