Regulated inverter using synchronized leading edge pulse width modulation

Claim 2

A regulated inverter comprising first and second transistors each having their collector-emitter paths connected with a source of input potential and at least a portion of the primary winding of a power transformer, a load coupled to the secondary winding of said power transformer, an error detector connected to said load to compare variations in said load voltage with a reference voltage, a feedback transformer having primary, secondary, and tertiary windings, a feedback network connected to the primary winding of said feedback transformer, means connecting the baseemitter paths of said first and second transistors to respectively equal portions of said secondary winding of said feedback transformer to drive said first and second transistors alternately between the conductive and nonconductive states in oscillation, switching means connected to the tertiary winding of said feedback transformer to divert the driving bias to the baseemitter paths of said first and second transistors from said secondary winding of said feedback transformer to said tertiary winding whenever said switching means is activated, an isolation transformer having primary and secondary windings, said primary winding of said isolation transformer being connected to said feedback network, modulating means connected to said switching means and said error detector to control the duration of the interval that said switching means is activated in accordance with load voltage variations, and means connecting said modulating means to said secondary winding of said isolation transformer to sense the initiation of each half cycle of driving bias in said feedback network and synchronize the activation of said switching means therewith while maintaining isolation between the higher power circuitry comprising said first and second inverter transistors and the relatively lower power circuitry of said modulating means.

Claim 3

A regulated inverter comprising first and second transistors having their collector-emitter paths connected with a source of input potential and equal portions of the primary winding of a power transformer, a load connected to the secondary winding of said power transformer, a feedback network comprising a third winding on said power transformer and a feedback transformer having primary, secondary, and tertiary windings, a resistor-inductor-capacitor series resonant network serially connected with the primary winding of said feedback transformer and said third winding on said power transformer, the base-emitter paths of said first and second transistors being connected to respectively equal portions of the secondary winding of said feedback transformer, switching means comprising a third transistor having its collector-emitter path connected across said tertiary winding of said feedback transformer to remove the driving bias to said first and second transistors whenever said third transistor is in deep conduction, a modulating control network connected to the base-emitter path of said third transistor to control conduction through said third transistor, said modulating control network including a fourth transistor having its base-emitter path coupled across said resistor in said series resonant circuit in said feedback network and its collector-emitter path connected with the base-emitter path of said third transistor to initiate conduction through said third transistor whenever the sinusoidal current in said feedback loop approaches its zero value, an error detector connected to said load to compare variations in load voltage with a reference voltage, a second capacitor connected to said error detector to be charged by the error signal output of said error detector, and means connected to said second capacitor and the base-emitter path of said third transistor to cutoff said third transistor when the charge on said capacitor reaches a predetermined value.

Claim 4

A regulated inverter comprising first and second transistors having their collector-emitter paths connected with a source of input potential and equal portions of the primary winding of a power transformer, a load connected to the secondary winding of said power transformer, a feedback network comprising a third winding on said power transformer and a feedback transformer having primary, secondary, and tertiary windings, a resistor-inductor-capacitor series resonant network serially connected with the primary winding of said feedback transformer and said third winding on said power transformer, the base-emitter paths of said first and second transistors being connected to respectively equal portions of the secondary winding of said feedback transformer, switching means comprising a third transistor having its collector-emitter path connected across said tertiary winding of said feedback transformer to remove the driving bias to said first and second transistors whenever said third transistor is in deep conduction, a modulating control network connected to the base-emitter path of said third transistor to control conduction through said third transistor, said modulating control network including a fourth transistor having its base-emitter path coupled across said resistor in said series resonant circuit in said feedback network and its collector-emitter path connected with the base-emitter path of said third transistor to initiate conduction through said third transistor whenever the sinusoidal current in said feedback loop approaches its zero value, an error detector connected to said load to compare variations in load voltage with a reference voltage, a second capacitor connected to said error detector to be charged by the error signal output of said error detector, and means connected to said second capacitor and the base-emitter path of said third transistor to cutoff said third transistor when the charge on said capacitor reaches a predetermined value.

Claim 5

A regulated inverter comprising first and second transistors each having their collector-emitter paths connected with a source of input potential and at least a portion of the primary winding of a power transformer, a load connected to the secondary winding of said power transformer, a feedback transformer having primary, secondary, and tertiary windings, a series resonant resistor-capacitor-inductor network serially connected with a feedback windiNg on said power transformer and the primary winding of said feedback transformer, means connecting the base-emitter paths of said first and second transistors to equal portions of the secondary winding of said feedback transformer to provide regenerative feedback bias to said transistors, an error detector connected to said load to compare variations in load voltage with a reference voltage and deliver an error signal output proportional to this difference, a third transformer having primary and secondary windings, means connecting the primary winding of said third transformer across said resistor of said series resonant resistor-capacitor-inductor circuit, a third transistor having its base-emitter path connected across the secondary winding of said third transformer to be responsive to the crossings on the time axis of the sinusoidal current in said series resistor-capacitor-inductor resonant circuit, a rectifier having its input terminals connected across the tertiary winding of said feedback transformer, a fourth transistor having its collector-emitter path connected across the output terminals of said bridge rectifier, means including a capacitor connecting the collector-emitter path of said third transistor to the base-emitter path of said fourth transistor to bias said fourth transistor into conduction each time the sinusoidal current through said series resistor-capacitor-inductor resonant network crosses the time axis, means connecting said error signal output from said error detector to said capacitor to charge said capacitor whenever said fourth transistor is biased into conduction, and means connected to said capacitor and the base-emitter path of said fourth transistor to be responsive to the magnitude of the charge on said capacitor so as to terminate conduction through said fourth transistor when the charge on said capacitor reaches a predetermined magnitude, whereby leading edge pulse width modulation is obtained.

Claim 6

A regulated inverter comprising first and second transistors each having their collector-emitter paths connected with a source of input potential and at least a portion of the primary winding of a power transformer, a load connected to the secondary winding of said power transformer, a feedback transformer having primary, secondary, and tertiary windings, a series resonant resistor-capacitor-inductor network serially connected with a feedback windiNg on said power transformer and the primary winding of said feedback transformer, means connecting the base-emitter paths of said first and second transistors to equal portions of the secondary winding of said feedback transformer to provide regenerative feedback bias to said transistors, an error detector connected to said load to compare variations in load voltage with a reference voltage and deliver an error signal output proportional to this difference, a third transformer having primary and secondary windings, means connecting the primary winding of said third transformer across said resistor of said series resonant resistor-capacitor-inductor circuit, a third transistor having its base-emitter path connected across the secondary winding of said third transformer to be responsive to the crossings on the time axis of the sinusoidal current in said series resistor-capacitor-inductor resonant circuit, a rectifier having its input terminals connected across the tertiary winding of said feedback transformer, a fourth transistor having its collector-emitter path connected across the output terminals of said bridge rectifier, means including a capacitor connecting the collector-emitter path of said third transistor to the base-emitter path of said fourth transistor to bias said fourth transistor into conduction each time the sinusoidal current through said series resistor-capacitor-inductor resonant network crosses the time axis, means connecting said error signal output from said error detector to said capacitor to charge said capacitor whenever said fourth transistor is biased into conduction, and means connected to said capacitor and the base-emitter path of said fourth transistor to be responsive to the magnitude of the charge on said capacitor so as to terminate conduction through said fourth transistor when the charge on said capacitor reaches a predetermined magnitude, whereby leading edge pulse width modulation is obtained.