Patent US3699537A successfully refreshed from Google Patents.
US3699537A
Expired / Lapsed
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Single-rail mosfet memory with capacitive storage
Assignee: Shell USA Inc
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Filing: 1970-09-08
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Granted: 1972-10-17
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Expires: 1990-09-08
Abstract
Abstract In connection with a one-device-per-bit capacitive MOSFET memory array, various topologies are disclosed for developing optimum memory storage capacitances between isolated P-regions and the fixed-potential substrate or a fixed-potential line. In particular, a fixed-potential line can be dispensed with, while retaining the improved capacitance associated therewith, by arranging the cells in pairs and cross-coupling them to one another. Particular clocking sequences and switching arrangements apposite to the cell topologies involved are also disclosed.
Inventors
- 👤 Sven E Wahlstrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:28
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/4074; G11C11/408; G11C11/409; G11C11/4094; G11C11/4096; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
77 words
In a capacitive memory array having a plurality of memory cells each consisting of a field-effect transistor whose gate electrode is connected to an address line and whose source-drain circuit is connected in series between bit line means and one side of a memory capacitance, the improvement comprising: grouping said memory cells in pairs, the memory capacitance of each cell of each pair being connected to the address line of the other cell of the same pair.
Claim 2
Dependent Claim
77 words
In a capacitive memory array having a plurality of memory cells each consisting of a field-effect transistor whose gate electrode is connected to an address line and whose source-drain circuit is connected in series between bit line means and one side of a memory capacitance, the improvement comprising: grouping said memory cells in pairs, the memory capacitance of each cell of each pair being connected to the address line of the other cell of the same pair.
Claim 3
Dependent Claim
27 words
The improvement of claim 1, in which the cells of each pair are physically adjacent and are connected to a common bit line means positioned between them.
References Cited (Backward Citations)
US3435138A
Cited
US3581292A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |