Adaptive data priority generator

Claim 2

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate with the data bus, each issuing a request signal when ready to communicate and starting communication upon receiving an answer signal from the data bus, comprising: a. a plurality of means for developing and storing a priority function, each associated with a data channel and adapted to vary the data channel''s priority function in response to its request signal and any data channel answer signal; and b. means for selecting the data channel issuing a request signal and having a priority function indicating the highest priority.

Claim 3

The apparatus of claim 1 wherein the means for developing and storing a priority function further includes means for decreasing the priority function over time.

Claim 4

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate wiTh the data bus, each data channel issuing a request signal when ready to communicate and starting communication upon receiving an answer signal from the data bus, comprising: a. a plurality of memory elements, each associated with a data channel and adapted to receive its request signals and answer signals, and further adapted to generate a set signal after receiving a request signal until receiving an answer signal; b. a plurality of means for accumulating and storing a priority function, each associated with a data channel, and responsive to the data channel''s set signal and any answer signal; and c. means for selecting the priority function indicating highest priority, from among the plurality of priority functions stored by said accumulating and storing means which are receiving set signals.

Claim 5

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate wiTh the data bus, each data channel issuing a request signal when ready to communicate and starting communication upon receiving an answer signal from the data bus, comprising: a. a plurality of memory elements, each associated with a data channel and adapted to receive its request signals and answer signals, and further adapted to generate a set signal after receiving a request signal until receiving an answer signal; b. a plurality of means for accumulating and storing a priority function, each associated with a data channel, and responsive to the data channel''s set signal and any answer signal; and c. means for selecting the priority function indicating highest priority, from among the plurality of priority functions stored by said accumulating and storing means which are receiving set signals.

Claim 6

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate with the data bus, each data channel issuing a request signal when ready to communicate and starting communication upon receiving an answer signal from the data bus, comprising: a. means associated with the data bus for generating a first signal in conjunction with said answer signals generated by said data bus; b. means associated with each data channel for receiving and accumulating said first signals when said data channel has issued a request signal; c. comparing means, responsive to all of said data channel receiving and accumulating means, for identifying the requesting channel having the largest accumulation of said first signals; and d. priority selection means associated with said data bus for allocating priority to said data channel identified by said comparing means.

Claim 7

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate with the data bus, each data channel issuing a request signal when ready to communicate and starting communication upon receiving an answer signal from the data bus, comprising: a. means associated with the data bus for generating a first signal in conjunction with said answer signals generated by said data bus; b. means associated with each data channel for receiving and accumulating said first signals when said data channel has issued a request signal; c. comparing means, responsive to all of said data channel receiving and accumulating means, for identifying the requesting channel having the largest accumulation of said first signals; and d. priority selection means associated with said data bus for allocating priority to said data channel identified by said comparing means.

Claim 8

Apparatus as claimed in claim 4 further comprising means associated with each data channel, and responsive to said data channel answer signal, for inhibiting the operation of said receiving and accumulating means a predetermined time after the arrival of said data channel answer signal and until said data channel''s request signal is again subsequently issued.

Claim 9

Apparatus as claimed in claim 5 further comprising means for decreasing the magnitude of said accumulated first signals as a function of time.

Claim 10

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate with the data bus, each issuing a request signal when ready to communicate, and starting communication upon receiving an answer signal from the data bus, comprising: a. a plurality of memory elements each receiving request signals from a data channel and answer signals for that data channel and generating a set signal after each request signal until an answer signal is received; b. a pulse generating system including a plurality of output pulse terminals, and a plurality of gating means for causing emission of pulses from a pulse terminal responsive to a set signal and any answer signal; c. a plurality of integrators, each receiving pulses from a pulse terminal, cumulatively forming the time integral of each pulse and decaying the value of the integral with time; and d. means for selecting, responsive to the set signals, a plurality of integrals, measuring the relative size of each integral, and generating a signal identifying the integrator storing the largest of these integrals.

Claim 11

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate with the data bus, each issuing a request signal when ready to communicate, and starting communication upon receiving an answer signal from the data bus, comprising: a. a plurality of memory elements each receiving request signals from a data channel and answer signals for that data channel and generating a set signal after each request signal until an answer signal is received; b. a pulse generating system including a plurality of output pulse terminals, and a plurality of gating means for causing emission of pulses from a pulse terminal responsive to a set signal and any answer signal; c. a plurality of integrators, each receiving pulses from a pulse terminal, cumulatively forming the time integral of each pulse and decaying the value of the integral with time; and d. means for selecting, responsive to the set signals, a plurality of integrals, measuring the relative size of each integral, and generating a signal identifying the integrator storing the largest of these integrals.

Claim 12

The apparatus of claim 7 wherein the pulse generating system and the plurality of integrators comprise a generator producing electrical pulses in response to answer signals; a plurality of AND gates each receiving the output of the pulse generator and a set signal; a plurality of capacitors, each receiving the output of an AND gate; and a plurality of impedances, each connected in parallel with a capacitor.

Claim 13

The apparatus of claim 8, including a plurality of means inserted between the AND gates and the capacitors, each having a low impedance to current pulses passing from the AND gateS to the capacitors, and a high reverse impedance.

Claim 14

The apparatus of claim 7 wherein each memory element comprises an electronic flip-flop responsive to a request signal and also responsive to an answer to the request signal.

Claim 15

The apparatus of claim 7 including a plurality of signal delay means, each connected to a memory element, and each receiving an answer signal and delaying its transmission to the memory elements until after the integrators have received the pulses from the pulse terminals.

Claim 16

The apparatus of claim 7 wherein each integrator comprises means for generating a voltage signal following the value of the integral.

Claim 17

The apparatus of claim 12 wherein said means for selecting the largest of said integrals further comprises: a. a plurality of first variable impedance means, each having a first power terminal, a second power terminal, and a control terminal receiving one of said output voltages causing the impedance of the variable impedance means to decrease if said voltage applied across the control terminal and the first power terminal is increased and increase if voltage so applied is decreased; b. first fixed impedance means having two terminals; c. first connecting means for connecting all the first power terminals to a terminal of the first fixed impedance means; d. a plurality of second fixed impedance means, one terminal of each connected to one of the second power terminals with the opposite terminals of all commonly connected; and e. a voltage source having one output terminal connected to the commonly connected terminal of the second fixed impedance means, and the second output terminal connected to the terminal of the first fixed impedance means common to the terminal of the integral holding means.

Claim 18

The apparatus of claim 13 wherein each of said variable impedance means comprises a transistor.

Claim 19

The apparatus of claim 13 including a plurality of second variable impedance means for receiving the outputs of the integrators and transmitting them to said respective first impedance means.

Claim 20

The apparatus of claim 15 wherein each of said second variable impedance means comprises a field effect transistor.

Claim 21

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate with the data bus, each issuing a request signal when ready to communicate and starting communication upon receiving an answer signal from the data bus, comprising: a. a plurality of means for developing and storing a priority function, each associated with a data channel and adapted to increase the indicated priority of the data channel''s priority function in response to its request signal and any data channel answer signal; and b. means for selecting the data channel issuing a request signal and having a priority function indicating the highest priority.

Claim 22

Apparatus for allocating priority of access to a data bus among a plurality of data channels simultaneously ready to communicate with the data bus, each issuing a request signal when ready to communicate and starting communication upon receiving an answer signal from the data bus, comprising: a. a plurality of means for developing and storing a priority function, each associated with a data channel and adapted to increase the indicated priority of the data channel''s priority function in response to its request signal and any data channel answer signal; and b. means for selecting the data channel issuing a request signal and having a priority function indicating the highest priority.

Claim 23

The apparatus of claim 17 wherein the means for developing and storing a priority function further includes means for decreasing the priority function over time.