US3568165A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Overrun protection circuit for a computing apparatus
Assignee: International Business Machines Corp
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Filing: 1969-01-14
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Granted: 1971-03-02
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Expires: 1989-01-14
Abstract
Abstract An overrun protection circuit for a computing apparatus having a plurality of I/O devices with predetermined load-operating characteristics operated in an overlap mode of operation. The overrun protection circuit includes a logic circuit at each I/O device and a test circuit at the CPU which provides a summation of load operating characteristics of all I/O devices operating in the computing apparatus at a predetermined instant and a comparison of such sum with a signal indicative of the maximum load-operating characteristic for the computer. The comparison signal determines whether the particular I/O device may be added to those operating in the computing apparatus at that instant and initiates operation in the logic circuit to accept or reject the operation request from the CPU.
Inventors
- 👤 John W Kerr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2289; G06F11/30; G06F11/34; G06F11/3466; G06F11/3485; G06F11/3442
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
421 words
An overrun protection circuit for a computing apparatus having a plurality of I/O devices with predetermined load capacity operating characteristics and a CPU connected to the I/O devices through a control channel for controlling the same comprising, control apparatus for each I/O device including means indicative that said I/O device has been selected for operation, said indicative means being a latch unit having a first signal input producing a predetermined output in response to a selection signal and a second signal input indicative of the completion of the operation of the I/O device which produces an absence of the output signal from the latch unit, means responsive to an operation instruction for said I/O device from the CPU, said means responsive to the instruction operation for said I/O device being an OR unit having a pair of inputs responsive to a test signal for operation of the I/O device or the start signal responsive to a start command for the I/O device, means connected to and responsive to the selection indicating means and the instruction operation means to provide an output signal indicative of the need for operation of said I/O device, said means responsive to the selection indication and instruction operation means being an AND unit, combining means including a summing amplifier having a plurality of input circuits each representative of the load capacity operating characteristics of the respective I/O device of the plurality of I/O devices and an output indicative of the total load capacity operating characteristics of the I/O devices in the computiNg apparatus which are in operation, means responsive to the means indicative of the need for operation of the respective I/O device to activate one of said plurality of input circuits of the combining means, said means responsive to the means indicative of the need of operation of the respective I/O device being an OR unit having a plurality of inputs and a fixed voltage signal output, comparator means including a reference load capacity characteristic signal indicative of the maximum load capacity of the computing apparatus connected to the combining means and responsive to its output to produce a signal indicative of the comparison of the output signal of the combining means and the reference signal, and command signal means connected to the means providing a signal indicative of the need for operation of the I/O device and the comparator means and providing selectively signals to the CPU to control a condition of operation of the respective I/O device in accord with the comparison output signal.
Claim 2
Dependent Claim
421 words
An overrun protection circuit for a computing apparatus having a plurality of I/O devices with predetermined load capacity operating characteristics and a CPU connected to the I/O devices through a control channel for controlling the same comprising, control apparatus for each I/O device including means indicative that said I/O device has been selected for operation, said indicative means being a latch unit having a first signal input producing a predetermined output in response to a selection signal and a second signal input indicative of the completion of the operation of the I/O device which produces an absence of the output signal from the latch unit, means responsive to an operation instruction for said I/O device from the CPU, said means responsive to the instruction operation for said I/O device being an OR unit having a pair of inputs responsive to a test signal for operation of the I/O device or the start signal responsive to a start command for the I/O device, means connected to and responsive to the selection indicating means and the instruction operation means to provide an output signal indicative of the need for operation of said I/O device, said means responsive to the selection indication and instruction operation means being an AND unit, combining means including a summing amplifier having a plurality of input circuits each representative of the load capacity operating characteristics of the respective I/O device of the plurality of I/O devices and an output indicative of the total load capacity operating characteristics of the I/O devices in the computiNg apparatus which are in operation, means responsive to the means indicative of the need for operation of the respective I/O device to activate one of said plurality of input circuits of the combining means, said means responsive to the means indicative of the need of operation of the respective I/O device being an OR unit having a plurality of inputs and a fixed voltage signal output, comparator means including a reference load capacity characteristic signal indicative of the maximum load capacity of the computing apparatus connected to the combining means and responsive to its output to produce a signal indicative of the comparison of the output signal of the combining means and the reference signal, and command signal means connected to the means providing a signal indicative of the need for operation of the I/O device and the comparator means and providing selectively signals to the CPU to control a condition of operation of the respective I/O device in accord with the comparison output signal.
Claim 3
Dependent Claim
114 words
The overrun protection circuit for a computing apparatus of claim 1 in which the comparator means is a voltage discriminator which compares the voltage due to the summation of all currents proportional to the total load capacity operating characteristic of all I/O devices operating at one time in the computing apparatus with a reference voltage representing 100 percent load for the computing apparatus and produces an output signal indicative of the relative magnitude of the summation of all of the load capacity operating characteristics of the I/O devices operating compared to the total permissive load capacity operating characteristics of I/O devices for the computer apparatus to be operating at a single period of time.
Claim 4
Dependent Claim
73 words
The overrun protection circuit for a computing apparatus of claim 2 in which the command signal means are a pair of AND units each connected to the responsive means providing the output signal indicative of the need for operation of said I/O device and the output of the comparator means to selectively indicate a signal to be fed back to the CPU indicative of the permissive condition of operation of said I/O device.
Claim 5
Dependent Claim
69 words
The overrun protection circuit for a computing apparatus of claim 3 and including a LATCH means connected to one of the AND units indicative of the condition that the instruction is accepted with the output of the LATCH unit being connected to the means activating one of the plurality of input circuits of the combining means to maintain said circuit activated during run operation of the said I/O device.
Claim 6
Dependent Claim
57 words
The overrun protection circuit for a computing apparatus of claim 4 and including additional circuit means connected to the LATCH means and the LATCH unit defining the means indicative that said I/O device has been selected for operation which additional circuits provide a reset signal for the LATCH units at completion of operation of the I/O device.
Claim 7
Dependent Claim
34 words
The overrun protection circuit for a computing apparatus of claim 5 in which the summation amplifier is of the analogue type and the comparator means is a voltage discriminator having a bilevel signal output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |