Peak detection circuits

Claim 2

A peak detection circuit, of the kind having a capacitive storage arrangement for storing a potential representative of the peak level of an input signal, including a first capacitive storage stage for storing a first potential represEntative of the peak level of the input signal and having a selected discharge time constant, a second capacitive storage stage, connected to the first stage, for storing a second potential representative of the peak input signal level, the second stage having a discharge time constant which is large relative to that of the first stage, means for comparing the first potential with a reference potential which is lower than the second potential, and means for reducing the discharge time constant of the second stage in response to decay of the first potential below the reference potential.

Claim 3

A peak detection circuit as claimed in claim 1 wherein the discharge time constant to which the second capacitive storage stage is reduced, when the potential stored by the first stage has decayed below said reference potential, is short relative to the discharge time constant of the first stage.

Claim 4

A peak detection circuit as claimed in claim 2 wherein the means for reducing the discharge time constant of the second capacitive storage stage when the potential stored by the first stage has decayed below said reference potential, includes a transistor which in dependence on the potential stored by the first stage, provides a relatively low impedance discharge path for the second stage.

Claim 5

A peak detection circuit as claimed in claim 2 including a feedback loop for feeding a signal level representative of the potential stored by the second capacitive storage stage to the first capacitive storage stage whereby the charging circuit for the said first stage becomes non-charging when the said signal level representative of the potential stored by the second stage exceeds the input signal level.

Claim 6

A peak detection circuit as claimed in claim 4 including a two-input comparator the said feedback loop and the input for said input signal each being connected to a respective input of the comparator and the comparator being connected to means for controlling the charging current of the first capacitive storage stage such that if the input signal is greater than the signal level on the feedback loop the means for controlling allows charging current to flow whereas if the input signal is lower than the feedback signal the means for controlling cuts off the charging current.

Claim 7

A peak detection circuit as claimed in claim 5 in which the said means for controlling the charging current comprises a transistor switch.

Claim 8

A peak detector circuit as claimed in claim 3 in which the said transistor is controlled by the output of a two input comparator, one input of which is fed with a potential representative of that stored by the first storage stage, and the other input of which is fed with a reference potential.

Claim 9

A peak detection circuit comprising, in combination; a first capacitive storage device; means for providing a fixed impedance discharge path to fixed potential for said first capacitive storage device and having, in combination therewith, a fixed discharge time constant; means for receiving a periodic input signal and for charging said first capacitive storage device in response to and to a peak voltage level related to the peak level of such input signal; a second capacitive storage device; high impedance amplifier means having an input connected to said first capacitive storage device for charging said second capacitive storage device to a voltage level related to said peak voltage level to which said first capacitive storage device is charged; variable impedance means for providing a discharge path to fixed potential for said second capacitive storage device; and means for comparing the instantaneous voltage level on said first capacitive storage device and for controlling said variable impedance means to provide a first discharge time constant for said second capacitive storage device which is long compared to said fixed discharge time constant when the instantaneous voltage level on said first capacitive storage device is above a selected value aNd to provide a second discharge time constant which is short compared to said fixed discharge time constant when said instantaneous voltage level decays below said selected value.

Claim 10

A peak detection circuit comprising, in combination; a first capacitive storage device; means for providing a fixed impedance discharge path to fixed potential for said first capacitive storage device and having, in combination therewith, a fixed discharge time constant; means for receiving a periodic input signal and for charging said first capacitive storage device in response to and to a peak voltage level related to the peak level of such input signal; a second capacitive storage device; high impedance amplifier means having an input connected to said first capacitive storage device for charging said second capacitive storage device to a voltage level related to said peak voltage level to which said first capacitive storage device is charged; variable impedance means for providing a discharge path to fixed potential for said second capacitive storage device; and means for comparing the instantaneous voltage level on said first capacitive storage device and for controlling said variable impedance means to provide a first discharge time constant for said second capacitive storage device which is long compared to said fixed discharge time constant when the instantaneous voltage level on said first capacitive storage device is above a selected value aNd to provide a second discharge time constant which is short compared to said fixed discharge time constant when said instantaneous voltage level decays below said selected value.