Self-checking combinational logic counter circuit

Claim 2

A count circuit for incrementing an input data word comprising a plurality of data bits and a parity bit, said count circuit comprising coding circuit means responsive to binary signals representing said data bits for generating coded output signals indicative of particular bits of said data bits to be changed, a first and a second parity predict circuit means for comparing said coded output signals and said binary signals to generate a first and a second parity change information signal, third parity predict circuit means responsive to said binary signals for generating a third parity change information signal, count logic circuit means responsive to said binary signals and said coded output signals for generating an output count comprising incremented data bits and responsive to a binary signal representing said parity bit and said third parity change information signal for generating a parity bit for said output count, and check logic circuit means for comparing said first, second, and third parity change information signals to generate an output signal indicating when said last-mentioned signals match.

Claim 3

A count circuit for incrementing an input count comprising a plurality of data bits and a parity bit, said count circuit comprising coding circuit means responsive to input binary signals representing said data bits for generating coded output signals indicative of particular bits of said data bits to be changed to form an output count, a first parity predict circuit means for comparing said coded output signals and said input binary signals to generate a first parity change information signal, a second parity predict ciRcuit means responsive to said input binary signals for generating a second parity change information signal, count logic circuit means responsive to said input binary signals and said coded output signals for generating an output count comprising incremented data bits, said count logic circuit means also responsive to a binary signal representing said parity bit and said second parity change information signal for generating a parity bit for said output count, and check logic circuit means for comparing said first and second parity change information signals to generate a fail signal when said last-mentioned signals fail to match.

Claim 4

A count circuit for incrementing an input count comprising a plurality of data bits and a parity bit, said count circuit comprising coding circuit means responsive to input binary signals representing said data bits for generating coded output signals indicative of particular bits of said data bits to be changed to form an output count, a first parity predict circuit means for comparing said coded output signals and said input binary signals to generate a first parity change information signal, a second parity predict ciRcuit means responsive to said input binary signals for generating a second parity change information signal, count logic circuit means responsive to said input binary signals and said coded output signals for generating an output count comprising incremented data bits, said count logic circuit means also responsive to a binary signal representing said parity bit and said second parity change information signal for generating a parity bit for said output count, and check logic circuit means for comparing said first and second parity change information signals to generate a fail signal when said last-mentioned signals fail to match.

Claim 5

A count circuit as claimed in claim 2 in which said coding circuit means and said second parity predict circuit means each comprises circuit means for detecting the rightmost consecutive binary ''''1s'''' in said data bits of said input count.

Claim 6

A counting circuit for incrementing an input data word comprising a plurality of binary data bits and a binary parity bit, said counting circuit comprising coding circuit means for detecting particular bits of said data bits to be complemented during said incrementing to generate a plurality of code bits indicative of said particular bits, first parity predict circuit means, responsive to said input data word, for predicting a change in parity during said incrementing and for generating a first parity change bit in accordance with said change, second parity predict circuit means, responsive to said input data word and said plurality of code bits, for predicting a change in parity during said incrementing and for generating a second parity change bit in accordance with said last-mentioned change, count logic circuit means for incrementing said data bits as determined by said code bits and for generating an output parity bit as determined by said first parity change bit, and check logic circuit means for comparing said first and said second parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 7

A counting circuit for incrementing an input data word comprising a plurality of binary data bits and a binary parity bit, said counting circuit comprising coding circuit means for detecting particular bits of said data bits to be complemented during said incrementing to generate a plurality of code bits indicative of said particular bits, first parity predict circuit means, responsive to said input data word, for predicting a change in parity during said incrementing and for generating a first parity change bit in accordance with said change, second parity predict circuit means, responsive to said input data word and said plurality of code bits, for predicting a change in parity during said incrementing and for generating a second parity change bit in accordance with said last-mentioned change, count logic circuit means for incrementing said data bits as determined by said code bits and for generating an output parity bit as determined by said first parity change bit, and check logic circuit means for comparing said first and said second parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 8

A counting circuit for incrementing an input data word comprising a plurality of binary data bits and a binary parity bit, said counting circuit comprising coding circuit means for detecting particular bits of said data bits to be complemented during said incrementing to generate a plurality of code bits corresponding to said binary data bits indicative of said particular bits, first parity predict circuit means for predicting a change in parity during said incrementing and for generating a first parity change bit in accordance with said change, second parity predict circuit means for predicting a change in parity in the even bits of said data bits during said incrementing as determined by the corresponding even bits of said code bits and for generating a second parity change bit in accordance with said last-mentioned change, third parity predict circuit means for predicting a change in parity in the odd bits of said data bits during said incrementing as determined by the corresponding odd bits of said code bits and for generating a third parity change bit in accordance with said last-mentioned change, count logic circuit means for incrementing said data bits as determined by said code bits and for generating an output parity bit as determined by said first parity change bit, and check logic circuit means for comparing said first, second, and third parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 9

A counting circuit for incrementing an input data word comprising a plurality of binary data bits and a binary parity bit, said counting circuit comprising coding circuit means for detecting particular bits of said data bits to be complemented during said incrementing to generate a plurality of code bits corresponding to said binary data bits indicative of said particular bits, first parity predict circuit means for predicting a change in parity during said incrementing and for generating a first parity change bit in accordance with said change, second parity predict circuit means for predicting a change in parity in the even bits of said data bits during said incrementing as determined by the corresponding even bits of said code bits and for generating a second parity change bit in accordance with said last-mentioned change, third parity predict circuit means for predicting a change in parity in the odd bits of said data bits during said incrementing as determined by the corresponding odd bits of said code bits and for generating a third parity change bit in accordance with said last-mentioned change, count logic circuit means for incrementing said data bits as determined by said code bits and for generating an output parity bit as determined by said first parity change bit, and check logic circuit means for comparing said first, second, and third parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 10

A self-checking counting circuit comprising a logic circuit for detecting in an input data word comprising a plurality of data bits and an input parity bit the rightmost binary bit of one value followed by a set of rightmost consecutive bits of the other value and for generating code bits indicative of said rightmost bits, a count logic circuit for logically combining said plurality of input data bits and said code bits to obtain an incremented data word, a first parity predict circuit means for detecting whether said set of riGhtmost consecutive bits is odd or even in number and for generating a first parity change bit in accordance therewith, logic circuit means for logically combining said input parity bit and said first parity change bit for generating a parity bit for said incremented data word, a second parity predict circuit means for logically combining said code bits and even numbered ones of said input data bits to obtain a second parity change bit, and check logic circuit means for comparing said first and second parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 11

A self-checking counting circuit comprising a logic circuit for detecting in an input data word comprising a plurality of data bits and an input parity bit the rightmost binary bit of one value followed by a set of rightmost consecutive bits of the other value and for generating code bits indicative of said rightmost bits, a count logic circuit for logically combining said plurality of input data bits and said code bits to obtain an incremented data word, a first parity predict circuit means for detecting whether said set of riGhtmost consecutive bits is odd or even in number and for generating a first parity change bit in accordance therewith, logic circuit means for logically combining said input parity bit and said first parity change bit for generating a parity bit for said incremented data word, a second parity predict circuit means for logically combining said code bits and even numbered ones of said input data bits to obtain a second parity change bit, and check logic circuit means for comparing said first and second parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 12

A self-checking counting circuit according to claim 6 also comprising a third parity predict circuit means for logically combining said code bits and odd numbered ones of said input data bits to obtain a third parity change bit, said check logic circuit means also comparing said third parity change bit with said first and second parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 13

In a data processing system, in combination, a source register containing a plurality of data bits and an initial parity bit, a coding logic circuit means for generating code bits indicative of the particular bits of a plurality of bits applied thereto which will be complemented during an incrementing operation, a count logic circuit means operated responsive to said code bits for incrementing data bits applied thereto, means for concurrently transferring said plurality of data bits to said coding logic circuit means and to said count logic circuit means to obtain an incremented output plurality of data bits, a first parity predict circuit means for predicting the parity of data bits applied thereto when incremented to generate a first parity change bit, means for applying said first parity change bit and said initial parity bit to said count logic circuit means concurrently with said plurality of data bits to generate an output parity bit, a second parity predict circuit means controlled by said code bits for predicting the parity of the odd positioned bits and of the even positioned bits of data bits applied thereto to generate a second and a third parity change bit, means for applying said plurality of data bits to said first and second parity predict circuit means concurrently with their application to said coding and count logic circuit means, means for transferring said output plurality of data bits and said output parity bit to a destination register, and check logic circuit means for comparing said first, second, and third parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 14

In a data processing system, in combination, a source register containing a plurality of data bits and an initial parity bit, a coding logic circuit means for generating code bits indicative of the particular bits of a plurality of bits applied thereto which will be complemented during an incrementing operation, a count logic circuit means operated responsive to said code bits for incrementing data bits applied thereto, means for concurrently transferring said plurality of data bits to said coding logic circuit means and to said count logic circuit means to obtain an incremented output plurality of data bits, a first parity predict circuit means for predicting the parity of data bits applied thereto when incremented to generate a first parity change bit, means for applying said first parity change bit and said initial parity bit to said count logic circuit means concurrently with said plurality of data bits to generate an output parity bit, a second parity predict circuit means controlled by said code bits for predicting the parity of the odd positioned bits and of the even positioned bits of data bits applied thereto to generate a second and a third parity change bit, means for applying said plurality of data bits to said first and second parity predict circuit means concurrently with their application to said coding and count logic circuit means, means for transferring said output plurality of data bits and said output parity bit to a destination register, and check logic circuit means for comparing said first, second, and third parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 15

A counting circuit comprising a coding logic circuit for generating a plurality of code bits indicative of changes between a plurality of input data bits and an increment of said data bits, a count logic circuit responsive to said code bits for incrementing said plurality of input data bits, a first parity predict circuit, responsive to said input data bits, for predicting the parity of said increment independently of said count logic to generate a first parity change bit in accordance therewith, a second parity predict circuit, responsive to said code bits and said input data bits, for predicting the parity of said increment dependent on said coding logic circuit to generate a second parity change bit in accordance therewith, and a check logic circuit for comparing said first and second parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 16

A counting circuit comprising a coding logic circuit for generating a plurality of code bits indicative of changes between a plurality of input data bits and an increment of said data bits, a count logic circuit responsive to said code bits for incrementing said plurality of input data bits, a first parity predict circuit, responsive to said input data bits, for predicting the parity of said increment independently of said count logic to generate a first parity change bit in accordance therewith, a second parity predict circuit, responsive to said code bits and said input data bits, for predicting the parity of said increment dependent on said coding logic circuit to generate a second parity change bit in accordance therewith, and a check logic circuit for comparing said first and second parity change bits to generate a fail signal when said last-mentioned bits fail to match.

Claim 17

A counting circuit as claimed in claim 9 in which said count logic circuit comprises means for comparing the parity of said plurality of input data bits and said first parity change bit for generating an output parity bit for said increment.