Patent US3699261A successfully refreshed from Google Patents.
US3699261A
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Frame synchronizing circuit for high clock frequency digital communication
Assignee: NEC Corp
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Filing: 1970-11-18
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Granted: 1972-10-17
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Expires: 1990-11-18
Abstract
Abstract A frame synchronizing circuit utilizes dual signal loops for inhibiting a clock pulse generator for a given time duration. The first loop includes a timing pulse generator a frame synchronous pulse detector, the set input of a bistable device an output thereof and two inhibit logic gates. The second loop control includes a synchronous pattern detector, delay means, and the reset input to the bistable device. Such dual control loop is useful in digital communication system operating at a high clock frequency in which loop delay time is not negligible.
Inventors
- 👤 Atsushi Tomozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:12
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608; H04L; H04L7/00; H04L7/04; H04L7/08
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
146 words
In a frame synchronizing circuit for digital communication comprising means for generating a detection pulse each time at least one pulse of a predetermined frame synchronizing pattern appears in the received digital pulse train, means for producing a tentative frame synchronizing pulse in each frame period, means for producing a discoincidence pulse each time said synchronizing pulse is non-coincident with said detection pulse, and means for inhibiting a required number of said clock pulses, the improvement which comprises: said inhibiting means including means for producing an output pulse having a width sufficient to inhibit said required number of said clock pulses, the wiDth of said output pulse being determined by the time difference between said discoincidence pulse and said detection pulse, means for supplying said discoincidence pulse to said output pulse producing means, and means for supplying said detection pulse to said output pulse producing means.
Claim 2
Dependent Claim
146 words
In a frame synchronizing circuit for digital communication comprising means for generating a detection pulse each time at least one pulse of a predetermined frame synchronizing pattern appears in the received digital pulse train, means for producing a tentative frame synchronizing pulse in each frame period, means for producing a discoincidence pulse each time said synchronizing pulse is non-coincident with said detection pulse, and means for inhibiting a required number of said clock pulses, the improvement which comprises: said inhibiting means including means for producing an output pulse having a width sufficient to inhibit said required number of said clock pulses, the wiDth of said output pulse being determined by the time difference between said discoincidence pulse and said detection pulse, means for supplying said discoincidence pulse to said output pulse producing means, and means for supplying said detection pulse to said output pulse producing means.
Claim 3
Dependent Claim
32 words
The improvement of claim 1, in which said output pulse producing means comprises a bistable circuit having a set terminal receiving said discoincidence pulse, and a reset terminal receiving said detection pulse.
Claim 4
Dependent Claim
31 words
The improvement of claim 2, in which detection pulse supplying means comprises delay means coupled between said detection pulse generating means and said reset terminal of said output pulse producing means.
Claim 5
Dependent Claim
31 words
The improvement of claim 3, in which said delay means provides a delay that is substantially equal to the time difference between said tentative frame synchronizing pulse and said output pulse.
Claim 6
Dependent Claim
28 words
The improvement of claim 1, in which said detection pulse supplying means comprises delay means coupled between said detection pulse generating means and said output pulse producing means.
Claim 7
Dependent Claim
31 words
The improvement of claim 5, in which said delay means provides a delay that is substantially equal to the time difference between said tentative frame synchronizing pulse and said output pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |