US3581010A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frame synchronization system for synchronizing the frame of a digital signal transmission
Assignee: Fujitsu Ltd
•
Filing: 1967-11-14
•
Granted: 1971-05-25
•
Expires: 1987-11-14
Abstract
Abstract A digital signal pulse train is supplied to a detector which detects the synchronous pattern of the pulse train. A pulse distributor distributes the digital signal pulse train under the control of the detected synchronous pattern by forcibly resetting the frame of the distributed digital signal pulses when the frame of the digital signal pulse train is nonsynchronous and providing a reset pulse for resetting itself independently of the forcible resetting at least once per frame of the digital signal pulse train. A gate circuit connected between the detector and the pulse distributor prohibits further forcible resetting of the pulse distributor until the next succeeding frame of the digital signal pulse train.
Inventors
- 👤 Toshio Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:35
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
326 words
A frame synchronization system for synchronization the frame of a digital signal transmission, comprising detecting means having an input and an output for detecting the synchronous pattern of a digital signal pulse train; input means connected to the input of said detecting means for supplying a digital signal pulse train to said detecting circuit; pulse-distributing means having a reset input, an input, a reset output and outputs constituting the outputs of said system and a reset input coupled to the output of said detecting means for distributing the digital signal pulse train under the control of the detected synchronous pattern by forcibly resetting the frame of the distributed digital signal pulses and for providing a reset pulse for resetting itself independently of the forcible resetting at least once per frame of said digital signal pulse train; and first gate means having an input connected to the reset output of the pulse-distributing means, an input connected to the output of the synchronous pattern-detecting circuit and an output coupled to the reset input of the pulse-distributing means for transferring the reset pulse provided by the pulsedistributing means from the reset output to the reset input of the pulse-distributing means when there is a zero signal in the output of the synchronous pattern-detecting circuit; a synchronism-protecting circuit having an input connected to the output of the first gate means and an output for providing output signals for enabling second gate means when input signals are provided at a density above a constant density; and second gate means having a first input connected to the output of the synchronous pattern-detecting circuit, a second input connected to the output of the synchronism-protecting circuit, an output coupled to the reset input of the pulse-distributing means, and a third input coupled to the output of said second gate means and to the output of said first gate means for prohibiting said second gate means from transmitting more than one reset pulse per frame.
Claim 2
Dependent Claim
326 words
A frame synchronization system for synchronization the frame of a digital signal transmission, comprising detecting means having an input and an output for detecting the synchronous pattern of a digital signal pulse train; input means connected to the input of said detecting means for supplying a digital signal pulse train to said detecting circuit; pulse-distributing means having a reset input, an input, a reset output and outputs constituting the outputs of said system and a reset input coupled to the output of said detecting means for distributing the digital signal pulse train under the control of the detected synchronous pattern by forcibly resetting the frame of the distributed digital signal pulses and for providing a reset pulse for resetting itself independently of the forcible resetting at least once per frame of said digital signal pulse train; and first gate means having an input connected to the reset output of the pulse-distributing means, an input connected to the output of the synchronous pattern-detecting circuit and an output coupled to the reset input of the pulse-distributing means for transferring the reset pulse provided by the pulsedistributing means from the reset output to the reset input of the pulse-distributing means when there is a zero signal in the output of the synchronous pattern-detecting circuit; a synchronism-protecting circuit having an input connected to the output of the first gate means and an output for providing output signals for enabling second gate means when input signals are provided at a density above a constant density; and second gate means having a first input connected to the output of the synchronous pattern-detecting circuit, a second input connected to the output of the synchronism-protecting circuit, an output coupled to the reset input of the pulse-distributing means, and a third input coupled to the output of said second gate means and to the output of said first gate means for prohibiting said second gate means from transmitting more than one reset pulse per frame.
Claim 3
Dependent Claim
127 words
A frame synchronization system as claimed in claim 1, further comprising flip-flop circuit means having an output, a set input and a reset input, and wherein the output of said second gate means is coupled to the said third input of said second gate means via said flip-flop circuit means and the output of said first gate means is coupled to said third input of said second gate means via said flip-flop circuit means, the output of said flip-flop circuit means being coupled to said third input of said second gate means, the set input of said flip-flop circuit being connected to the output of said second gate means and the reset input of said flip-flop circuit being connected to the output of said first gate means.
Claim 4
Dependent Claim
39 words
A frame synchronization system is claimed in claim 2, further comprising time delay means, and wherein the output of said flip-flop circuit means is coupled to said third input of said second gate means via said time delay means.
Claim 5
Independent Claim
107 words
A method of synchronizing the frame of a digital signal transmission, comprising the steps of detecting the synchronous pattern of a digital signal pulse train; distributing the digital signal pulse train under the control of the detected synchronous pattern; forcibly resetting the frame of the distributed digital signal pulses when the frame of the digital signal pulse train is nonsynchronous; resetting the frame of the distributed digital signal pulses under clock control at least once per frame of the digital signal train; and prohibiting further forcible resetting of the frame of the distributed digital signal pulses until the next succeeding frame of the digital signal pulse train.
Claim 6
Independent Claim
107 words
A method of synchronizing the frame of a digital signal transmission, comprising the steps of detecting the synchronous pattern of a digital signal pulse train; distributing the digital signal pulse train under the control of the detected synchronous pattern; forcibly resetting the frame of the distributed digital signal pulses when the frame of the digital signal pulse train is nonsynchronous; resetting the frame of the distributed digital signal pulses under clock control at least once per frame of the digital signal train; and prohibiting further forcible resetting of the frame of the distributed digital signal pulses until the next succeeding frame of the digital signal pulse train.
Claim 7
Dependent Claim
45 words
A method of synchronizing the frame of a digital signal transmission as claimed in claiM 4, further comprising a determining when the detected synchronous pattern is in a time slot preceding the synchronous position and forcibly resetting the frame of the distributed digital signal pulses.
Claim 8
Dependent Claim
45 words
A method of synchronizing the frame of a digital signal transmission as claimed in claim 4, further comprising determining when the detected synchronous pattern is in a time slot subsequent to its synchronous position and forcibly resetting the frame of the distributed digital signal pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |