US3698080A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for forming low impedance ohmic attachments
Assignee: General Electric Co
•
Filing: 1970-11-02
•
Granted: 1972-10-17
•
Expires: 1990-11-02
Abstract
Abstract A plurality of semiconductor wafers each containing a junction are plated with aluminum on an N conductivity type surface and stacked between P conductivity type attachment wafers. The stack is heated to bond the wafers, gold is plated onto the endmost wafers, and excess aluminum at the periphery of the stack is removed. The wafer stack is subdivided first into slabs and then the slabs repositioned to close the kerf formed by sawing. The repositioned slabs are then subdivided into unitary dice stacks. The unitary dice stacks are then attached to gold coated leads and freed of surface contaminants by flow etching. The cleaned unitary dice stacks are separately protectively encapsulated to form completed rectifiers by first depositing a passivant over the semiconductive surfaces and then molding a plastic housing around the elements.
Inventors
- 👤 Warren E Berner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:23
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W72/00; H10W90/00; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/02
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
82 words
A process according to claim 1 in which the semiconductive stack is formed by stacking a plurality of separate semiconductive crystals, bonding metal is interposed between adjacent stacked crystals, the bonding metal is brought to its melting temperature to form a tenacious, low impedance bond between adjacent crystals, and to bond the crystals into a unitary structure, removing at least a portion of the bonding metal lying peripherally of the unitary stack, and sawing the unitary stack to form the semiconductive means.
Claim 2
Dependent Claim
67 words
A process according to claim 1 in which the one electrical conductor bonded to the first interconnection surface of the semiconductive means includes a second spacing semiconductive element identical to the first recited spacing semiconductive element and the second spacing semiconductive element Is bonded to the first interconnection surface simultaneous with bonding the first recited spacing semiconductive element to the second interconnection surface of the semiconductive stack.
Claim 3
Dependent Claim
220 words
A process comprising intimately associating with one major surface of a first conductivity characteristic of each of a plurality of semiconductive wafers containing at least one junction and presenting an opposed major surface of a second conductivity characteristic a metal, bondable to both major surfaces and having a greater readiness to bond to the opposed major surfaces of the second conductivity characteristic, stacking the junction-containing wafers with the one major surface of each junction-containing wafer facing the opposed major surface of the next adjacent junction-containing wafer, stacking adjacent a major surface of an endmost of the junction-containing wafers a junctionless attachment semiconductive wafer of conductivity opposite to said major surface, bonding the wafers into a unitary stack, subdividing the stack to form a plurality of separately useable stack portions, bonding to a first interconnection surface provided by a portion of the attachment wafer contained in the stack portion and to a second interconnection surface provided by a portion of an endmost junction-containing wafer remote from the attachment wafer portion respective electrical conductors using a bonding material readily adherent to surfaces of the conductivity characteristic of the attachment wafer portion, said last recited bonding step producing an ohmic connection between each conductor and the adjacent semiconductor material, etching the stack portion to remove surface contaminants, and protectively encapsulating the stack portion.
References Cited (Backward Citations)
US2798989A
Cited
US3503125A
Cited
US3290760A
Cited
US3369290A
Cited
US3333324A
Cited
US3422527A
Cited
US3416046A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |