Geometry for a pnp silicon transistor with overlay contacts

Claim 2

A semiconductor device which comprises a semiconductor wafer of a first conductivity type having a major surface, a first region of a second conductivity type within said wafer and extending to said surface, a second region of said first conductivity type within said first region and extending to said surface, a third region within said wafer noncontiguously surrounding said first region and extending to said surface, said third region being of the same conductivity type as said wafer but of a lower resistivity, a protective refractory coating on said surface over said regions, at least one island within said third region having a relatively thick protective coating thereon as compared to the coating on said third region, said third region having a discontinuity therein generally coextensive with said island, said discontinuity having conductivity determining impurities therein consisting essentially of the same dopants in the same concentrations as in wafer portions contiguous other parts of said third region, a terminal connector contact on said island in electrical communication with one of said first and second regions, and a terminal connector lead pressure bonded to the contact on said thick protective coating.

Claim 3

A semiconductor device which comprises a semiconductor wafer of a first conductivity type having a major surface, a first region of a second conductivity type within said wafer and extending to said surface, a second region of said first conductivity type within said first region and extending to said surface, a third region within said wafer noncontiguously surrounding said first region and extending to said surface, said third region being of the same conductivity type as said wafer but of a lower resistivity, a protective refractory coating on said surface over said regions, at least one island within said third region having a relatively thick protective coating thereon as compared to the coating on said third region, said third region having a discontinuity therein generally coextensive with said island, said discontinuity having conductivity determining impurities therein consisting essentially of the same dopants in the same concentrations as in wafer portions contiguous other parts of said third region, a wire bond contact pad on said island in electrical communication with one of said first and second regions, and a connector wire pressure bonded to the contact pad on said thick protective coating.

Claim 4

A semiconductor device which comprises a semiconductor wafer of a first conductivity type having a major surface, a first region of a second conductivity type within said wafer and extending to said surface, a second region of said first conductivity type within said first region and extending to said surface, a third region within said wafer noncontiguously surrounding said first region and extending to said surface, said third region being of the same conductivity type as said wafer but of a lower resistivity, a protective refractory coating on said surface over said regions, at least one island within said third region having a relatively thick protective coating thereon as compared to the coating on said third region, said third region having a discontinuity therein generally coextensive with said island, said discontinuity having conductivity determining impurities therein consisting essentially of the same dopants in the same concentrations as in wafer portions contiguous other parts of said third region, a wire bond contact pad on said island in electrical communication with one of said first and second regions, and a connector wire pressure bonded to the contact pad on said thick protective coating.

Claim 5

A semiconductor device which comprises a semiconductor high resistivity wafer of a first conductivity type having a major surface, a first region of a second conductivity type within said wafer and extending to said surface, a second region of said first conductivity type within said first region and extending to said surface, a third region within said wafer noncontiguously surrounding said second region and extending to said surface, said third region being of the same conductivity type as said wafer but of lower resistivity, a protective coating of silicon oxide on said surface over said regions, spaced apart island-like discontinuities in said third region on said wafer surface, each of said discontinuities having conductivity determining impuritIes therein consisting essentially of the same dopants in the same concentration as in wafer portions contiguous other parts of said third region, a relatively thick silicon oxide coating over the discontinuities in said region as compared to the balance of said coating overlying said third region, a wire bond contact pad on each of said islands, one of said contact pads in electrical communication with said first region, another of said contact pads in electrical communication with said second region, and connector wires pressure bonded to said pads on said thicker oxide coating.

Claim 6

A semiconductor device which comprises a semiconductor high resistivity wafer of a first conductivity type having a major surface, a first region of a second conductivity type within said wafer and extending to said surface, a second region of said first conductivity type within said first region and extending to said surface, a third region within said wafer noncontiguously surrounding said second region and extending to said surface, said third region being of the same conductivity type as said wafer but of lower resistivity, a protective coating of silicon oxide on said surface over said regions, spaced apart island-like discontinuities in said third region on said wafer surface, each of said discontinuities having conductivity determining impuritIes therein consisting essentially of the same dopants in the same concentration as in wafer portions contiguous other parts of said third region, a relatively thick silicon oxide coating over the discontinuities in said region as compared to the balance of said coating overlying said third region, a wire bond contact pad on each of said islands, one of said contact pads in electrical communication with said first region, another of said contact pads in electrical communication with said second region, and connector wires pressure bonded to said pads on said thicker oxide coating.

Claim 7

A semiconductor device which comprises a P-type silicon wafer having a major surface, an N-type region within said wafer extending to said surface, a P-type region within said N-type region extending to said surface, a P-type border of said wafer surrounding said N-type region on said surface, a P+ region within said wafer noncontiguously surrounding said N-type region closely spaced therefrom and extending to said surface, said P+ region having spaced apart island-like discontinuities through which islands of P-type wafer material extend to said surface, said discontinuities having conductivity determining impurities consisting essentially of the same dopants in the same concentration as in wafer portions contiguous other parts of said third region, a silicon oxide coating on said surface, the oxide coating on said islands being thicker than on said P+ region, wire bond contact pads on said thicker oxide coating, one of said contact pads in electrical communication with said N-type region, another of said contact pads in electrical communication with said P-type region within said N-type region, and connector wires pressure bonded to said pads on said thicker oxide coating.

Claim 8

A semiconductor device which comprises a P-type silicon wafer having a major surface, an N-type region within said wafer extending to said surface, a P-type region within said N-type region extending to said surface, a P-type border of said wafer surrounding said N-type region on said surface, a P+ region within said wafer noncontiguously surrounding said N-type region closely spaced therefrom and extending to said surface, said P+ region having spaced apart island-like discontinuities through which islands of P-type wafer material extend to said surface, said discontinuities having conductivity determining impurities consisting essentially of the same dopants in the same concentration as in wafer portions contiguous other parts of said third region, a silicon oxide coating on said surface, the oxide coating on said islands being thicker than on said P+ region, wire bond contact pads on said thicker oxide coating, one of said contact pads in electrical communication with said N-type region, another of said contact pads in electrical communication with said P-type region within said N-type region, and connector wires pressure bonded to said pads on said thicker oxide coating.

Claim 9

A PNP transistor which comprises a P-type silicon wafer forming a transistor collector region having a major surface, an N-type base region within said collector region and extending to said surface, a P-type emitter region within said base region and extending to said surface, a guard ring within collector region noncontiguously surrounding said base region and extending to said surface, a portion of said collector region intersecting said surface between said base region and said guard ring, said guard ring extending from said collector portion to the periphery of said surface, spaced apart islands of said collector region extending to said surface within island-like discontinuities in said guard ring, said islands having conductivity determining impurities consisting essentially of P-type dopants in the same concentration as in collector portions contiguous other parts of said guard ring, a silicon oxide coating on said surface, a thicker silicon oxide coating over said islands than over said guard ring, overlay contacts each having bonding contact pads on said thicker oxide coating, one of said contacts in electrical communication with said emitter region, another of said contacts in electrical communication with said base region, and connector wires pressure bonded to each of said contact pads on said thicker oxide coating.

Claim 10

A PNP transistor which comprises a P-type silicon wafer forming a transistor collector region having a major surface, an N-type base region within said collector region and extending to said surface, a P-type emitter region within said base region and extending to said surface, a guard ring within collector region noncontiguously surrounding said base region and extending to said surface, a portion of said collector region intersecting said surface between said base region and said guard ring, said guard ring extending from said collector portion to the periphery of said surface, spaced apart islands of said collector region extending to said surface within island-like discontinuities in said guard ring, said islands having conductivity determining impurities consisting essentially of P-type dopants in the same concentration as in collector portions contiguous other parts of said guard ring, a silicon oxide coating on said surface, a thicker silicon oxide coating over said islands than over said guard ring, overlay contacts each having bonding contact pads on said thicker oxide coating, one of said contacts in electrical communication with said emitter region, another of said contacts in electrical communication with said base region, and connector wires pressure bonded to each of said contact pads on said thicker oxide coating.

Claim 11

A PNP transistor which comprises a P-type silicon wafer forming a transistor collector region having a major surface, an N-type base region within said collector region and extending to said surface, a P-type emitter region within said base region and extending to said surface, a guard ring within collector region noncontiguously surrounding said base region and extending to said surface, a portion of said collector region intersecting said surface between the guard ring and the base region, said collector portion spacing said base region about 0.001 inches from said guard ring, said guard extending from said collector portion to the periphery of said surface, spaced apart islands of said collector region extending to said surface within island-like discontinuities in said guard ring on opposite sides of said base region, said islAnds having conductivity determining impurities consisting essentially of P-type dopants in the same concentration as in collector portions contiguous other parts of said guard ring, a silicon oxide coating on said surface, a thicker silicon oxide coating over sad islands than over said guard ring, evaporated aluminum overlay contacts each having bonding contact pads on said thicker oxide coating, one of said contacts in electrical communication with said emitter region, another of said contacts in electrical communication with said base region, and connector wires pressure bonded to each of said contact pads on said thicker oxide coating.

Claim 12

A PNP transistor which comprises a P-type silicon wafer forming a transistor collector region having a major surface, an N-type base region within said collector region and extending to said surface, a P-type emitter region within said base region and extending to said surface, a guard ring within collector region noncontiguously surrounding said base region and extending to said surface, a portion of said collector region intersecting said surface between the guard ring and the base region, said collector portion spacing said base region about 0.001 inches from said guard ring, said guard extending from said collector portion to the periphery of said surface, spaced apart islands of said collector region extending to said surface within island-like discontinuities in said guard ring on opposite sides of said base region, said islAnds having conductivity determining impurities consisting essentially of P-type dopants in the same concentration as in collector portions contiguous other parts of said guard ring, a silicon oxide coating on said surface, a thicker silicon oxide coating over sad islands than over said guard ring, evaporated aluminum overlay contacts each having bonding contact pads on said thicker oxide coating, one of said contacts in electrical communication with said emitter region, another of said contacts in electrical communication with said base region, and connector wires pressure bonded to each of said contact pads on said thicker oxide coating.

Claim 13

A semiconductor device which comprises a face bonded semiconductor wafer, said wafer being of a first conductivity type and having a major surface, a first region of a second conductivity type within said wafer and extending to said surface, a second region of said first conductivity type within said first region and extending to said surface, a third region within said wafer noncontiguously surrounding said second region and extending to said surface, said third region being of the same conductivity type as said wafer but of lower resistivity, a protective refractory coating on said surface over said regions, spaced apart island-like discontinuities in said third region on said wafer surface, each of said discontinuities having conductivity determining impurities therein consisting essentially of the same dopants in the same concentration as in wafer portions contiguous other parts of said third region, a relatively thick protective refractory coating over the discontinuities in said region as compared to the balance of said coating overlying said third region, a contact pad on each of said islands, one of said contact pads in electrical communication with said fist region, another of said contact pads in electrical communication with said second region, an enlarged connector element on each of said contact pads, and each connector element in contact with a terminal connector lead.

Claim 14

A semiconductor device which comprises a face bonded semiconductor wafer, said wafer being of a first conductivity type and having a major surface, a first region of a second conductivity type within said wafer and extending to said surface, a second region of said first conductivity type within said first region and extending to said surface, a third region within said wafer noncontiguously surrounding said second region and extending to said surface, said third region being of the same conductivity type as said wafer but of lower resistivity, a protective refractory coating on said surface over said regions, spaced apart island-like discontinuities in said third region on said wafer surface, each of said discontinuities having conductivity determining impurities therein consisting essentially of the same dopants in the same concentration as in wafer portions contiguous other parts of said third region, a relatively thick protective refractory coating over the discontinuities in said region as compared to the balance of said coating overlying said third region, a contact pad on each of said islands, one of said contact pads in electrical communication with said fist region, another of said contact pads in electrical communication with said second region, an enlarged connector element on each of said contact pads, and each connector element in contact with a terminal connector lead.

Claim 15

A face-bonded transistor wafer which comprises a high resistivity P-type silicon wafer having a major surface, an N-type base region within said wafer extending to said surface, a P-type emitter region within said N-type region extending to said surface, a P+ region within said P-type wafer noncontiguously closely surrounding said N-type region and extending to said surface, the outer extremity of said P+ region extending to the periphery of said surface, said P+ region having two discontinuities therein forming two spaced apart islands in which the high resistivity P-type silicon extends to said surface, said islands having conductivity determining impurities consisting essentially of P-type dopants in the same concentration as in wafer portions contiguous other parts of said P+ region, a silicon oxide coating on said surface, the oxide coating on said islands being thicker than on said P+ region, contact pads on said thicker oxide coating, one of said contact pads in electrical communication with said N-type region, another of said contact pads in electrical communication with said P-type region within said N-type region, an enlarged contact bump on each contact pad, and each contact bump pressure bonded and soldered to a connecting terminal lead.

Claim 16

A face-bonded transistor wafer which comprises a high resistivity P-type silicon wafer having a major surface, an N-type base region within said wafer extending to said surface, a P-type emitter region within said N-type region extending to said surface, a P+ region within said P-type wafer noncontiguously closely surrounding said N-type region and extending to said surface, the outer extremity of said P+ region extending to the periphery of said surface, said P+ region having two discontinuities therein forming two spaced apart islands in which the high resistivity P-type silicon extends to said surface, said islands having conductivity determining impurities consisting essentially of P-type dopants in the same concentration as in wafer portions contiguous other parts of said P+ region, a silicon oxide coating on said surface, the oxide coating on said islands being thicker than on said P+ region, contact pads on said thicker oxide coating, one of said contact pads in electrical communication with said N-type region, another of said contact pads in electrical communication with said P-type region within said N-type region, an enlarged contact bump on each contact pad, and each contact bump pressure bonded and soldered to a connecting terminal lead.