Planar semiconductor devices

Claim 1

A PLANAR TRANSISTOR COMPRISING: A DIE OF SEMICONDUCTOR MATERIAL HAVING A COLLECTOR REGION OF ONE CONDUCTIVITY TYPE, AT LEAST A PORTION OF SAID COLLECTOR REGION BEING CONTIGUOUS WITH A GIVEN SURFACE OF SAID DIE; A BASE REGION OF OPPOSITE CONDUCTIVITY TYPE INSET INTO SAID COLLECTOR REGION, THE SURFACE OF SAID BASE REGION BEING CONTIGUOUS WITH SAID GIVEN SURFACE; AN EMITTER REGION OF SAID ONE CONDUCTIVITY TYPE INSET INTO SAID BASE REGION, THE SURFACE OF SAID EMITTER REGION BEING CONTIGUOUS WITH SAID GIVEN SURFACE; A LAYER OF INSULTING MATERIA ON SAID GIVEN SURFACE HAVING APERTURES THEREIN TO EXPOSE GIVEN PARTS OF SAID BASE AND EMITTER REGIONS; A METALLIC LAYER ON SAID LAYER OF INSULATING MATERIAL OVERLYING THE CONTIGUOUS PORTION OF SAID COLLECTOR REGION AND CONTACTING A GIVEN ONE OF SAID EMITTER AND BASE REGIONS THROUGH A CORRESPONDING ONE OF SAID APERTURES; AND AN AUXIALIARY REGION OF SAID OPPOSITE CONDUCTIVITY TYPE INSET INTO AND SURROUNDED BY SAID COLLECTOR REGION, THE SURFACE OF SAID AUXIALIARY REGION BEING CONTIGUOUS WITH SAID GIVEN SURFACE AND UNDERLYING SAID METALLIC LAYER THEREBY TO REDUCED THE CAPACITANCE BETWEEN SAID METALIC LAYER AND SAID COLLECTOR REGION.