Monolithic memory system with bi-level powering for reduced power consumption

Claim 2

A bilevel powered random access monolithic memory system comprising: a supporting substrate, an X, Y matrix of monolithic integrated semiconductor chips supported on said substrate, each of said chips comprising an array of bistable memory cells and supporting circuitry for selecting and addressing cells in said array, means for maintaining said chips in a low standby power state comprising means for applying a low bias voltage across each of the cells in each of the chips, and means for raising a selected chip in said matrix to a high power state by changing the X voltage level applied to a line of chips in the X direction and changing the Y voltage level applied to a line of chips in the Y direction to raise the chip at the intersection of the X and Y lines to the high power state, each of the cells in the chip arrays comprising a pair of transistors cross-coupled to form a bistable cell capable of storing one binary bit of information during the standby power state, said cells requiring a change in voltage level applied to the collectors and a change in voltage level applied to the emitters of said cross-coupled transistors in order to be addressed, and said supporting circuitry including connection means for utilizing the change in X voltage level and the change in Y voltage level to respectively change the voltage levels applied to the collectors and emitters of the cross-coupled transistors in the row of cells in said array selected for addressing on the selected chip to raise the voltage across each of the cells in said selected row to a higher voltage level.

Claim 3

The monolithic memory system of claim 1 wherein each of said cells comprises a pair of transistors each having two emitters, one of emitters of each transistor being connected to that of the other transistor, said change in voltage level being applied to the connected emitters.

Claim 4

A monolithic memory system comprising an integrated circuit chip comprising an array of bistable cells arranged along lines in the horizontal and vertical directions and supporting circuitry, means for maintaining the array in a low power state comprising means for applying a low bias voltage across each of the cells in each of said chips, means providing a first voltage level, means providing a second voltage level, each of the cells in the array comprising a pair of transistors cross-coupled to form a bistable cell capable of storing one binary bit of information, said support circuitry comprising a plurality of gating means, each associated with and operative to selectively connect through connecting means said first and second voltage levels to the cells along one of the lines in said array, each of said gating means being adapted to receive a binary data signal pattern input and an intermittent gating signal and to selectively connect said voltage levels to the line of storage elements associated with said gating means only upon receiving the gating signal and a preselected data signal pattern input, decoDing means for receiving a pattern of binary signals representative of a selection of one of said lines in the array and for applying to the gating means associated with said selected line the preselected data signal pattern input required for the gating means to connect said first and second level to said selected line, means for simultaneously applying an intermittent gating signal to each of said gating means, and means for intermittently applying power to said decoding means for periods in correlation with the application of said gating signal whereby said gating signal and said data signal pattern inputs are coincidentally applied to said gates, said connecting means connecting said first and second voltage levels respectively to the collectors and emitters of the cross-coupled transistors in the cells of the selected line to bring said cells into the high power state, and said connecting means including delay means for delaying the application of the second voltage level until after said first voltage level has been applied and for delaying the removal of said first level until after the second level has been removed.

Claim 5

A monolithic memory system comprising an integrated circuit chip comprising an array of bistable cells arranged along lines in the horizontal and vertical directions and supporting circuitry, means for maintaining the array in a low power state comprising means for applying a low bias voltage across each of the cells in each of said chips, means providing a first voltage level, means providing a second voltage level, each of the cells in the array comprising a pair of transistors cross-coupled to form a bistable cell capable of storing one binary bit of information, said support circuitry comprising a plurality of gating means, each associated with and operative to selectively connect through connecting means said first and second voltage levels to the cells along one of the lines in said array, each of said gating means being adapted to receive a binary data signal pattern input and an intermittent gating signal and to selectively connect said voltage levels to the line of storage elements associated with said gating means only upon receiving the gating signal and a preselected data signal pattern input, decoDing means for receiving a pattern of binary signals representative of a selection of one of said lines in the array and for applying to the gating means associated with said selected line the preselected data signal pattern input required for the gating means to connect said first and second level to said selected line, means for simultaneously applying an intermittent gating signal to each of said gating means, and means for intermittently applying power to said decoding means for periods in correlation with the application of said gating signal whereby said gating signal and said data signal pattern inputs are coincidentally applied to said gates, said connecting means connecting said first and second voltage levels respectively to the collectors and emitters of the cross-coupled transistors in the cells of the selected line to bring said cells into the high power state, and said connecting means including delay means for delaying the application of the second voltage level until after said first voltage level has been applied and for delaying the removal of said first level until after the second level has been removed.

Claim 6

The monolithic memory system of claim 3 wherein each of the cell comprises a pair of transistors each having two emitters, one of the emitters of each transistor being connected to that of the other transistor, said second voltage level being applied to the connected emitters.

Claim 7

In a random access memory system having an array of bistable storage elements arranged along lines in the horizontal and vertical directions, addressing means for selectively applying a selected voltage level to the storage elements along one of said lines comprising: means providing said selected voltage level, a plurality of gating means, each associated with and operative to selectively connect said voltage level to the storage elements along a different one of said lines in one of said directions, each of said gating means being adapted to receive a binary data signal pattern input and an intermittent gating signal and to selectively connect said voltage level to the line of storage elements associated with said gating means only upon receiving the gating signal coincidentally with a preselected data signal pattern input, decoding means including means for receiving a pattern of binary signals representative of a selection of one of said lines in said one direction, means, responsive to the application of an intermittent high power level input to the decoding means, for applying to only the gating means associated with said selected line the preselected data signal pattern input required for the gating means to connect said voltage level to said selected line, and means for applying, to each of said plurality of gating means, during the periods when said intermittent high power level input is not being applied, the respective preselected data signal pattern input required for each gating means to connect said voltage level to the line associated with each respective gating means, means for simultaneously applying an intermittent gating signal to each of said gating means, and means for intermittently applying a high power level input to said decoding means for periods in correlation with the application of said gating signal so that said gating signal is applied during the application of said high power level input, at which time the preselected data signal pattern required to connect said voltage level to said selected line is being applied only to the gating means associated with said selected line.

Claim 8

In a random access memory system having an array of bistable storage elements arranged along lines in the horizontal and vertical directions, addressing means for selectively applying a selected voltage level to the storage elements along one of said lines comprising: means providing said selected voltage level, a plurality of gating means, each associated with and operative to selectively connect said voltage level to the storage elements along a different one of said lines in one of said directions, each of said gating means being adapted to receive a binary data signal pattern input and an intermittent gating signal and to selectively connect said voltage level to the line of storage elements associated with said gating means only upon receiving the gating signal coincidentally with a preselected data signal pattern input, decoding means including means for receiving a pattern of binary signals representative of a selection of one of said lines in said one direction, means, responsive to the application of an intermittent high power level input to the decoding means, for applying to only the gating means associated with said selected line the preselected data signal pattern input required for the gating means to connect said voltage level to said selected line, and means for applying, to each of said plurality of gating means, during the periods when said intermittent high power level input is not being applied, the respective preselected data signal pattern input required for each gating means to connect said voltage level to the line associated with each respective gating means, means for simultaneously applying an intermittent gating signal to each of said gating means, and means for intermittently applying a high power level input to said decoding means for periods in correlation with the application of said gating signal so that said gating signal is applied during the application of said high power level input, at which time the preselected data signal pattern required to connect said voltage level to said selected line is being applied only to the gating means associated with said selected line.

Claim 9

The random access memory system of claim 5 wherein said array is a monolithic integrated semiconductor array of a plurality of cells, each in one of two bistable states.

Claim 10

The memory system of claim 6 wherein each of the cells in said array comprises a pair of transistors cross-coupled to form a bistable cell capable of storing one binary bit of information, said selected voltage level being applied to collectOrs of the cross-coupled transistors in the selected line, and said system further includes means for providing a second voltage level, means controlled by said gating means, for applying said second voltage level to the emitters of the cross-coupled transistors in the selected line coincidentally with the connection of the selected level to the collectors, said means for applying the second level including delay means for delaying the application of the second voltage level until after said selected voltage level has been applied and for delaying the removal of said selected level until after the second level has been removed.

Claim 11

The memory system of claim 7 wherein each of the cells comprises a pair of transistors each having two emitters, one of the emitters of each transistor being connected to that of the other transistor, said second voltage level being applied to the connected emitters.

Claim 12

The system of claim 6 wherein each of said gating means has a plurality of input terminal to which the binary data signal pattern input is applied and the preselected signal pattern input is one in which each of the signals applied to each of the input terminals is in the same binary state.

Claim 13

The system of claim 9 wherein the gating means are AND gates, each having a plurality of input terminals to which the binary data signal pattern input is applied and the preselected signal pattern input comprises a binary '''' 1'''' applied to each input terminal.

Claim 14

The system of claim 10 wherein the decoding means comprise a plurality of true-complement generators adapted to receive a signal pattern comprising a plurality of parallel binary bits representative of the selected line to which said voltage level is to be connected, each of said binary bits being applied to a different one of said generators and each of said generators producing a two terminal output respectively representing the true applied bit and its complement and interconnection means for connecting the true output terminals and complement terminals of each generator to one of the input terminals in a different plurality of said AND gates, said true and complement output terminals being connected to AND gate input terminals in such a manner that each of the AND gates has its input terminals connected to a different combination of generator output terminals, each of said generators producing a true-complement binary output only when said power is applied to said decoding means and a binary ''''1'''' output on each of its terminals during the period when power is not being applied.

Claim 15

The system of claim 11 wherein each of said true-complement generators comprises a pair of common emitter transistors, the collector of one being connected to the base of the other whereby one of the transistors must be non-conductive when the other is conductive, the output of one of said transistor being the true output terminal and the output of the other transistor being the complement output terminal each of said transistors being non-conductive when said power is not being applied to provide a binary ''''1'''' on both the true and complement output terminals and only one of said transistors being selectively rendered conductive when said power is applied to drop the output of said transistor to a binary ''''0'''', the selection of the transistor rendered conductive being dependent on state of the binary bit applied to said generator.