US3688128A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arrangement for decoding a four-level signal
Assignee: US Philips Corp
•
Filing: 1971-03-25
•
Granted: 1972-08-29
•
Expires: 1991-03-25
Abstract
Abstract A device for decoding a four-level signal comprising two mutually connected digital circuits which are each provided with a current source and an associated switching member so as to connect the current source to an output impedance associated with the relevant digital circuit, the switching member associated with one digital circuit responding to a previously determined amplitude value of the input signal applied to the two digital circuits, and the switching member associated with the other digital circuit responding to a certain first or second amplitude value of the input signal dependent on the position of the switching member of the first digital circuit.
Inventors
- 👤 Hendrik Arie Van Essen
- 👤 Arie Slob
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:36
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L5/00; H04L5/02; H04L5/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
214 words
A decoder for a four-level signal, comprising first and second digital circuits, each of said first and said second digital circuits comprising a current source, a switching means, and an output load impedance, a common input circuit for applying the four-level signal to the input means of the first and the second digital circuits, first reference voltage level means coupled to the first digital circuit, and means interconnecting the first and the second digital circuits, said switching means of said first digital circuit connecting said current source of said first digital circuit to said output load impedance of said first digital circuit for a four-level input signal of a predetermined first amplitude level with respect to said first reference voltage level, said first digital circuit generating second and third reference voltage levels in correspondence to the amplitude of the four-level input signal, said second and said third reference voltage level means being coupled to said second digital circuit by said interconnecting means, said switching means of said second digital circuit connecting said current source of said second digital circuit to said output load impedance of said second digital circuit for a four-level input signal of a predetermined second or third amplitude level with respect to said second or said third reference voltage levels respectively.
Claim 2
Dependent Claim
214 words
A decoder for a four-level signal, comprising first and second digital circuits, each of said first and said second digital circuits comprising a current source, a switching means, and an output load impedance, a common input circuit for applying the four-level signal to the input means of the first and the second digital circuits, first reference voltage level means coupled to the first digital circuit, and means interconnecting the first and the second digital circuits, said switching means of said first digital circuit connecting said current source of said first digital circuit to said output load impedance of said first digital circuit for a four-level input signal of a predetermined first amplitude level with respect to said first reference voltage level, said first digital circuit generating second and third reference voltage levels in correspondence to the amplitude of the four-level input signal, said second and said third reference voltage level means being coupled to said second digital circuit by said interconnecting means, said switching means of said second digital circuit connecting said current source of said second digital circuit to said output load impedance of said second digital circuit for a four-level input signal of a predetermined second or third amplitude level with respect to said second or said third reference voltage levels respectively.
Claim 3
Dependent Claim
47 words
A decoder as claimed in claim 1, wherein each of said switching means comprises a pair of transistors in a common emitter configuratIon, each of said output load impedance being in series with the collector of one of said transistors in each of said respective transistor pairs.
Claim 4
Dependent Claim
101 words
A decoder as claimed in claim 2, wherein said common input circuit is connected to the base of a transistor in one transistor pair and to the base of a transistor in the other transistor pair, said first reference voltage level being coupled to the base of the other transistor in said one transistor pair, said second and said third reference voltage levels being coupled to the base of the other transistor of said other transistor pair, said second and third voltage levels being generated in correspondence to conducting and non-conducting of one of the transistors in said one transistor pair.
Claim 5
Dependent Claim
35 words
A decoder as claimed in claim 3, wherein said interconnecting means connects the collector of said other transistor in said one transistor pair to the base of said other transistor of said other transistor pair.
Claim 6
Dependent Claim
30 words
A decoder as claimed in claim 2, wherein each of said transistor pairs comprises a circuit for connecting the collector of one transistor to the base of the other transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-29 | 1976-02-28 | 1976-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-29 | 1980-02-28 | 1980-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-29 | 1984-02-28 | 1984-08-29 | $7700.00 | Window Closed / Lapsed |