Frequency detector

Claim 1

Electronic apparatus for detecting gross shifts in the frequency of electronic oscillators employed in time-fuse weapon systems comprising in combination: first and second parallel accumulators each comprising a five stage flip-flop wherein the true output of each flip-flop is connected to the trigger input of the succeeding flip-flop; means coupling a standard electronic oscillator to the trigger input of the first flip-flop of said five stage flip-flop of the first accumulator whereby the first accumulator accumulates pulses; a first AND gate having its inputs coupled to the false outputs of the fIrst, fourth, and fifth flip-flop of the first accumulator; a first NAND gate; a signal indicating means; a second AND gate having one input coupled to the output of the first AND gate and another input coupled to the output of the first NAND gate and its output coupled to the signal indicating means for providing an indicating signal when said first AND gate is enabled by the output of said first accumulator, said first NAND gate having one input coupled to a false output of the fifth flip-flop and another input coupled to the false output of the fourth flip-flop of the second accumulator; means coupling an electronic oscillator of a fuse to the trigger input of the first flip-flop of the five stage flip-flop of said second accumulator whereby the second accumulator accumulates pulses; a third AND gate having its inputs coupled to the false output of the first, fourth, and fifth flip-flops of said second accumulator; and a second NAND gate a fourth AND gate having one input coupled to the output of a second NAND gate and its output coupled to said means for producing an indicating signal when said third AND gate is enabled by the output of the second accumulator, said second NAND gate having one input coupled to a false output of the fifth flip-flop and another input coupled to the false output of the fourth flip-flop of the first accumulator; said fourth and fifth flip-flops of the first accumulator adapted not to switch their false outputs when less than 24 pulses have been admitted to the first accumulator during the time when 25 pulses have been admitted to the second accumulator whereupon the output of the second NAND gate provides a ''''one'''' input to the fourth AND gate, and said first, fourth, and fifth flip-flops of the second accumulator switching their false outputs to ''''ones'''' whereby the third AND gate is enabled providing a second input to the fourth AND gate which in response thereto the said means for providing an indicating signal is enabled indicating an undesired discrepancy in fuse oscillator frequency.