Frequency difference detector

Claim 3

Apparatus for determining the difference between the number of pulses in two series of electricaL pulses comprising: means for generating first and second series of electrical pulses; means for sensing the pulses in said first and second series of electrical pulses; a counter; and circuit means for applying pulses in said first series of electrical pulses to said counter during successive time intervals each commenced by the sensing of a predetermined plurality of pulses in said first series of electrical pulses and terminated by the sensing of the same predetermined plurality of pulses in said second series of electrical pulses.

Claim 4

Apparatus for determining the difference between the number of pulses in two series of electricaL pulses comprising: means for generating first and second series of electrical pulses; means for sensing the pulses in said first and second series of electrical pulses; a counter; and circuit means for applying pulses in said first series of electrical pulses to said counter during successive time intervals each commenced by the sensing of a predetermined plurality of pulses in said first series of electrical pulses and terminated by the sensing of the same predetermined plurality of pulses in said second series of electrical pulses.

Claim 5

The apparatus of claim 2 wherein said circuit means includes means for disabling the sensing of pulses in said first series of electrical pulses upon the commencement of each of said time intervals and for enabling the sensing of pulses in said first series of electrical pulses upon the termination of each of said time intervals.

Claim 6

The apparatus of claim 2 wherein said circuit means includes a pair of registers each connected respectively to receive pulses in said first and second series of electrical pulses and gate means for passing pulses in said first series of electrical pulses to said counter when enabled and for otherwise blocking the passage of pulses in said first series of electrical pulses to said counter, said gate means being enabled by the storage of said predetermined plurality of pulses in said first register and disabled by the storage of said predetermined plurality of pulses in said second register, both of said registers being cleared upon the disabling of said gate means.

Claim 7

The apparatus of claim 2 including a second counter and second circuit means for applying pulses in said second series of electrical pulses to said second counter during successive time intervals each commenced by the sensing of a predetermined plurality of pulses in said second series of electrical pulses and terminated by the sensing of the same plurality of pulses in the first series of electrical pulses.

Claim 8

Apparatus for measuring the difference in the number of pulses in two series of electrical pulses comprising: first and second sources of electrical pulses; first and second storage means; a first output terminal for indicating the difference in the number of pulses from said sources of electrical pulses when the number of pulses from said first source of electrical pulses is greater than the number of pulses from said second source of electrical pulses; a second output terminal for indicating the difference in the number of pulses from said sources of electrical pulses when the number of pulses from said source of electrical pulses is greater than the number of pulses from said first source of electrical pulses; first circuit means for applying pulses from said first source to said first output terminal and to said first storage means; said first circuit means including first gate means for passing pulses from said first source of electrical pulses to said first output terminal when enabled and for otherwise blocking the passage of pulses from said first source of electrical pulses to said first output terminal, and first blocking means for making said first storage means nonresponsive to pulses from said first source of electrical pulses; said first storage means being connected to said first gate means and to said first blocking means for enabling said gate means and blocking said storage means in response to the accumulation of a predetermined plurality of pulses from said first source of electrical pulses in said first storage means; second circuit means including second gate means for passing pulses from said second source of electrical pulses to said second output terminal when enabled and for otherwise blocking the passage of pulses from said second source of electrical pulses to said second output terminal, and second blocking means for making said second storage means nonresponsive to pulses from said second source of electrical pulses; said second storagE means being connected to said second gate means and to said second blocking means for enabling said gate means and blocking said storage means in response to the accumulation of said predetermined plurality of pulses from said second source of electrical pulses in said second storage means; and reset means connected to said first and second storage means, said first and second gate means, and said first and second blocking means for clearing said first and second storage means, disabling said first and second gate means, and unblocking said first and second blocking means.

Claim 9

Apparatus for measuring the difference in the number of pulses in two series of electrical pulses comprising: first and second sources of electrical pulses; first and second storage means; a first output terminal for indicating the difference in the number of pulses from said sources of electrical pulses when the number of pulses from said first source of electrical pulses is greater than the number of pulses from said second source of electrical pulses; a second output terminal for indicating the difference in the number of pulses from said sources of electrical pulses when the number of pulses from said source of electrical pulses is greater than the number of pulses from said first source of electrical pulses; first circuit means for applying pulses from said first source to said first output terminal and to said first storage means; said first circuit means including first gate means for passing pulses from said first source of electrical pulses to said first output terminal when enabled and for otherwise blocking the passage of pulses from said first source of electrical pulses to said first output terminal, and first blocking means for making said first storage means nonresponsive to pulses from said first source of electrical pulses; said first storage means being connected to said first gate means and to said first blocking means for enabling said gate means and blocking said storage means in response to the accumulation of a predetermined plurality of pulses from said first source of electrical pulses in said first storage means; second circuit means including second gate means for passing pulses from said second source of electrical pulses to said second output terminal when enabled and for otherwise blocking the passage of pulses from said second source of electrical pulses to said second output terminal, and second blocking means for making said second storage means nonresponsive to pulses from said second source of electrical pulses; said second storagE means being connected to said second gate means and to said second blocking means for enabling said gate means and blocking said storage means in response to the accumulation of said predetermined plurality of pulses from said second source of electrical pulses in said second storage means; and reset means connected to said first and second storage means, said first and second gate means, and said first and second blocking means for clearing said first and second storage means, disabling said first and second gate means, and unblocking said first and second blocking means.

Claim 10

The apparatus of claim 6 wherein said reset means includes multivibrator means triggered when the last of said fist and second storage means to accumulate said predetermined plurality of pulses accumulates said predetermined plurality of pulses.

Claim 11

The apparatus of claim 6 wherein said reset means includes a coincidence gate connected to said first and second storage means for receiving signals generated in response to the accumulation of said predetermined plurality of pulses in said first and second storage means.

Claim 12

The apparatus of claim 3 wherein said circuit means includes a pair of registers each connected respectively to receive pulses in said first and second series of electrical pulses and gate means for passing pulses in said first series of electrical pulses to said counter when enabled and for otherwise blocking the passage of pulses in said first series of electrical pulses to said counter, said gate means being enabled by the storage of said predetermined plurality of pulses in said first register and disabled by the storage of said predetermined plurality of pulses in said second register, both of said registers being cleared upon the disabling of said gate means.

Claim 13

The apparatus of claim 7 wherein said reset means includes a coincidence gate connected to said first and second storage means for receiving signals generated in response to the accumulation of said predetermined plurality of pulses in said first and second storage means.

Claim 14

Apparatus for measuring the difference in the number of pulses in two series of electrical pulses comprising: first and second sources of electrical pulses; first and second storage means; an output terminal for indicating the difference in the number of pulses from said sources of electrical pulses when the number of pulses from said first source of electrical pulses is greater than the number of pulses from said second source of electrical pulses; circuit means for applying pulses from said first source to said output terminal and to said first storage means; said circuit means including gate means for passing pulses from said first source of electrical pulses to said output terminal when enabled and for otherwise blocking the passage of pulses from said first source of electrical pulses to said output terminal, and blocking means for making said first storage means nonresponsive to pulses from said first source of electrical pulses; said first storage means being connected to said gate means and to said blocking means for enabling said gate means and blocking said first storage means in response to the accumulation of a predetermined plurality of pulses from said first source of electrical pulses in said first storage means; and reset means connected to said first and second storage means, said gate means, and said blocking means for clearing said first and second storage means, disabling said gate means, and unblocking said blocking means in response to the accumulation of a like plurality of pulses from said second source of electrical pulses in said second storage means.

Claim 15

Apparatus for measuring the difference in the number of pulses in two series of electrical pulses comprising: first and second sources of electrical pulses; first and second storage means; an output terminal for indicating the difference in the number of pulses from said sources of electrical pulses when the number of pulses from said first source of electrical pulses is greater than the number of pulses from said second source of electrical pulses; circuit means for applying pulses from said first source to said output terminal and to said first storage means; said circuit means including gate means for passing pulses from said first source of electrical pulses to said output terminal when enabled and for otherwise blocking the passage of pulses from said first source of electrical pulses to said output terminal, and blocking means for making said first storage means nonresponsive to pulses from said first source of electrical pulses; said first storage means being connected to said gate means and to said blocking means for enabling said gate means and blocking said first storage means in response to the accumulation of a predetermined plurality of pulses from said first source of electrical pulses in said first storage means; and reset means connected to said first and second storage means, said gate means, and said blocking means for clearing said first and second storage means, disabling said gate means, and unblocking said blocking means in response to the accumulation of a like plurality of pulses from said second source of electrical pulses in said second storage means.

Claim 16

The apparatus of claim 11 wherein said reset means includes multivibrator means triggered when said second storage means accumulates said predetermined plurality of pulses and a coincidence gate connected to said first and second storage means for receiving signals generated in response to the accumulation of said predetermIned plurality of pulses in said first and second storage means.