Read-write circuit for capacitive memory arrays

Claim 2

A read-write circuit for capacitive memories, comprising: a. a plurality of memory elements each connected to one half of a halved bit line; b. cross-coupled sensing amplifier means arranged to operate in a race mode between the two bit line halves; c. means for selectively impressing only a logic ''''0'''' onto one of said bit line halves in response to the occurrence of a writing signal, such means being characterized in that a logic ''''1'''' is not impressed onto either of the bit line halves by a writing signal; and d. means responsive to the address of the addressed memory element and to the logic state of the data to be written for selecting the bit line half onto which said logic ''''0'''' is to be impressed.

Claim 3

The circuit of claim 1, in which said sensing circuit means and said logic ''''0'''' impressing means consist of MOSFET circuitry.

Claim 4

The circuit of claim 1, in which said last-named means iNclude a source of logic ''''0'''' potential, and a pair of gate means each connected between said source and one of said bit line halves, and means for enabling one of said gate means when a logic ''''1'''' is to be written and for enabling the other of said gate means when a logic ''''0'''' is to be written.

Claim 5

A sensing arrangement for capacitive MOSFET memories, comprising: a. a plurality of individually addressable capacitive memory elements each connected to one half of a halved bit line; b. cross-coupled, high-impedance sensing amplifier means connected to the two halves of said bit line and arranged to operate in a race mode between them so as to provide a dual-rail sensing amplifier output indicative of the information stored in the addressed memory element; c. output amplifier means including cross-coupled MOSFET means arranged to operate in a race mode between a pair of nodes; d. a source of read strobe pulses; and e. a pair of MOSFET switching means connecting said source of read strobe pulses to said pair of nodes; f. said sensing amplifier output being connected to the gate electrodes of said MOSFET switching means and g. said output amplifier means being dimensioned and arranged to drive low-impedance output line gating means.

Claim 6

A sensing arrangement for capacitive MOSFET memories, comprising: a. a plurality of individually addressable capacitive memory elements each connected to one half of a halved bit line; b. cross-coupled, high-impedance sensing amplifier means connected to the two halves of said bit line and arranged to operate in a race mode between them so as to provide a dual-rail sensing amplifier output indicative of the information stored in the addressed memory element; c. output amplifier means including cross-coupled MOSFET means arranged to operate in a race mode between a pair of nodes; d. a source of read strobe pulses; and e. a pair of MOSFET switching means connecting said source of read strobe pulses to said pair of nodes; f. said sensing amplifier output being connected to the gate electrodes of said MOSFET switching means and g. said output amplifier means being dimensioned and arranged to drive low-impedance output line gating means.

Claim 7

The arrangement of claim 4, further including low-impedance data output line means operatively connected to said output amplifier means and having gating means arranged to be selectively enabled; and means for selectively enabling said data output line gating means, said means for selectively enabling including a pair of logic elements whose output is responsive both to the logic state of one of said bit line halves, respectively, and to said Xn and Xn address components, respectively.

Claim 8

The circuit of claim 5 in which said logic elements are a pair of NOR gates, each of which have one input operatively connected to one of said nodes, another input operatively connected to a source of Xn or Xn signals, respectively, and an output connected to the gate electrode of one of said data output line gating means.

Claim 9

A low-impedance data output circuit for capacitive MOSFET memories having a plurality of selectively addressable memory cells, comprising: a. a MOSFET sensing amplifier having a high-impedance, double-rail output; b. cross-coupled output amplifier means arranged to operate in a race mode between a pair of nodes; c. means operatively connecting each rail of said double-rail output to one of said nodes; and d. low-impedance data output line means including gating means enabled in accordance with the logic state of a selected one of said nodes.

Claim 10

A low-impedance data output circuit for capacitive MOSFET memories having a plurality of selectively addressable memory cells, comprising: a. a MOSFET sensing amplifier having a high-impedance, double-rail output; b. cross-coupled output amplifier means arranged to operate in a race mode between a pair of nodes; c. means operatively connecting each rail of said double-rail output to one of said nodes; and d. low-impedance data output line means including gating means enabled in accordance with the logic state of a selected one of said nodes.

Claim 11

The circuit of claim 7, in which said data output line gating means are enabled by a pair of logic elements whose output is responsive both to the logic state of said double-rail output and to the address of the addressed memory cell.

Claim 12

The circuit of claim 8 in which said logic elements are a pair of NOR gates whose inputs include inputs connected, respectively, to one of said nodes and to an address component of said memory cells.

Claim 13

The circuit of claim 7, in which said rail-to-node connecting means include a source of read strobe pulses and switching means operated by the output of said sensing amplifier to selectively apply said read strobe pulses to one or the other of said pair of nodes.

Claim 14

The circuit of claim 7, in which there are a plurality of sensing amplifiers, and in which said rail-to-node connecting means further include means for selectively operatively connecting the output of any selected one of said sensing amplifiers to the nodes of said output amplifier.

Claim 15

A sensing arrangement for capacitive MOSFET memories, comprising: a. a plurality of selectively addressable memory cells each containing a memory capacitance; b. a pair of bit line halves each associated with one-half of said plurality of memoRy cells and each having a bit line capacitance large as compared to said memory capacitance; c. addressing means for connecting a selected one of said memory capacitances to the bit line half associated with it so as to produce a voltage variation therein under predetermined circumstances; d. a sensing amplifier arranged to sense a voltage difference between said bit line halves and to produce an output representative of the sign of said difference; e. precharge means for precharging both bit line halves to the same voltage prior to addressing one of said memory cells; and f. preconditioning means arranged to produce in one of said bit line halves a voltage variation of approximately one-half the voltage variation produced in the other bit line half by the connection of a memory capacitance thereto.

Claim 16

A sensing arrangement for capacitive MOSFET memories, comprising: a. a plurality of selectively addressable memory cells each containing a memory capacitance; b. a pair of bit line halves each associated with one-half of said plurality of memoRy cells and each having a bit line capacitance large as compared to said memory capacitance; c. addressing means for connecting a selected one of said memory capacitances to the bit line half associated with it so as to produce a voltage variation therein under predetermined circumstances; d. a sensing amplifier arranged to sense a voltage difference between said bit line halves and to produce an output representative of the sign of said difference; e. precharge means for precharging both bit line halves to the same voltage prior to addressing one of said memory cells; and f. preconditioning means arranged to produce in one of said bit line halves a voltage variation of approximately one-half the voltage variation produced in the other bit line half by the connection of a memory capacitance thereto.

Claim 17

The arrangement of claim 12, in which said preconditioning means include a pair of sources of preconditioning pulses, means capacitively coupling each of said sources of preconditioning pulses to one of said bit line halves, and means for causing said preconditioning pulses to occur only at the source associated with the bit line half opposite the one to which the addressed memory capacitance is being connected.

Claim 18

The arrangement of claim 12, in which said preconditioning means include a pair of preconditioning cells, one on each bit line half, said preconditioning cells including a preconditioning capacitance having approximately one-half the capacitance of one of said memory capacitances, and including means for precharging said preconditioning capacitances, and means for connecting each of said preconditioning capacitances to its bit line half whenever a memory cell on the other bit line half is being addressed.

Claim 19

A level-restoring sensing amplifier arrangement for capacitive MOSFET memories, comprising: a. a plurality of selectively addressable memory capacitances; b. a pair of bit line halves each associated with one half of said plurality of memory capacitances and adapted to be connected to an addressed memory capacitance; c. cross-coupled MOSFET sensing amplifier means connected to said bit line halves and arranged to operate in a race mode; and d. level-restoring means associated with said bit line halves, said level-restoring means including i. a source of level-restoring pulses; and ii. MOSFET gating means arranged to connect said source of level-restoring pulses to said bit lines, the ''''on'''' resistance of said MOSFET gating means being so related to the ''''on'''' resistance of the race MOSFETS of said sensing amplifier as to produce a below-threshold voltage on the bit line half which is at logic ''''0'''' following the race.

Claim 20

A level-restoring sensing amplifier arrangement for capacitive MOSFET memories, comprising: a. a plurality of selectively addressable memory capacitances; b. a pair of bit line halves each associated with one half of said plurality of memory capacitances and adapted to be connected to an addressed memory capacitance; c. cross-coupled MOSFET sensing amplifier means connected to said bit line halves and arranged to operate in a race mode; and d. level-restoring means associated with said bit line halves, said level-restoring means including i. a source of level-restoring pulses; and ii. MOSFET gating means arranged to connect said source of level-restoring pulses to said bit lines, the ''''on'''' resistance of said MOSFET gating means being so related to the ''''on'''' resistance of the race MOSFETS of said sensing amplifier as to produce a below-threshold voltage on the bit line half which is at logic ''''0'''' following the race.