Patent US3676775A successfully refreshed from Google Patents.
US3676775A
Expired / Lapsed
US
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Method for measuring resistivity
Assignee: International Business Machines Corp
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Filing: 1971-05-07
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Granted: 1972-07-11
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Expires: 1991-05-07
Abstract
Abstract The method for measuring the bulk resistivity of an epitaxial semiconductor layer on a monocrystalline semiconductor base with a 4-point probe apparatus wherein the base has at least two high conductivity diffused regions, positioning two current probes directly over two separate diffused regions in contact with the surface of the epitaxial layer, placing two spaced voltage probes in contact with the epitaxial layer in a generally intermediate position relative to the current probes, inducing a current through the current probes and measuring the voltage drop between the voltage probes, calculating the bulk resistivity in accordance with the expression:
Inventors
- 👤 Andrew Dupnock
- 👤 Edward F Gorey
- 👤 William A Keenan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/2607; G01R31/2637; G01N; G01N27/00; G01N27/02; G01N27/04; G01N27/041
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
171 words
A method of measuring the bulk resistivity of an epitaxial semiconductor layer on a monocrystalline semiconductor base with a 4-point probe apparatus comprising, forming at least two-spaced high conductivity diffused regions in the base, depositing an epitaxial layer of semiconductor material on the base, positioning two current probes directly over said diffused regions in contact with the surface of said epitaxial layer, placing two-spaced voltage probes in contact with the surface of said epitaxial layer in generally intermediate positions relative said current probes, introducing through said current probes an electrical current flow through the epitaxial layer between the probes, measuring the voltage drop in the epitaxial layer across said voltage probes, calculating the bulk resistivity in accordance with the expression: Resistivity V/I X C.F. X t, where V is the voltage drop, I is the current flow, t is the epitaxial layer thickness, and dC.F. is an empirical correction factor that is a function of the voltage probe spacing and the percent area of the substrate covered by the diffused regions.
Claim 2
Independent Claim
171 words
A method of measuring the bulk resistivity of an epitaxial semiconductor layer on a monocrystalline semiconductor base with a 4-point probe apparatus comprising, forming at least two-spaced high conductivity diffused regions in the base, depositing an epitaxial layer of semiconductor material on the base, positioning two current probes directly over said diffused regions in contact with the surface of said epitaxial layer, placing two-spaced voltage probes in contact with the surface of said epitaxial layer in generally intermediate positions relative said current probes, introducing through said current probes an electrical current flow through the epitaxial layer between the probes, measuring the voltage drop in the epitaxial layer across said voltage probes, calculating the bulk resistivity in accordance with the expression: Resistivity V/I X C.F. X t, where V is the voltage drop, I is the current flow, t is the epitaxial layer thickness, and dC.F. is an empirical correction factor that is a function of the voltage probe spacing and the percent area of the substrate covered by the diffused regions.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein said voltage probes are placed over two separate sub-surface high conductivity diffused regions in said base.
Claim 4
Dependent Claim
31 words
The method of claim 2 wherein said base and overlying semiconductor layer includes a plurality of subsurface high conductivity diffused regions intermediate said diffused regions beneath the current and voltage probes.
Claim 5
Dependent Claim
32 words
The method of claim 3 wherein said diffused regions under said voltage and current probes are tests sites on a wafer at an intermediate stage in the fabRication of integrated circuit devices.
Claim 6
Dependent Claim
21 words
The method of claim 1 wherein said thickness of the epitaxial layer is in the range of 0.2 to 15 microns.
Claim 7
Dependent Claim
11 words
The method of claim 1 wherein said semiconductor material is silicon.
References Cited (Backward Citations)
US3609537A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-11 | 1976-01-10 | 1976-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-11 | 1980-01-10 | 1980-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-11 | 1984-01-10 | 1984-07-11 | $7700.00 | Window Closed / Lapsed |