Vector half-angle computer

Claim 1

An analog computing device for providing from first and second input signals representative of input quadrature component vectors, first and second output signals representative of quadrature component vectors of a sum vector having the same magnitude but one-half of the angle of the sum vector of said input quadrature component vectors, said device comprising: signal generator means for generating first and second gating signals at a first frequency and third and fourth gating signals at a second frequency equal to twice said first frequency, said first and second gating signals being in phase quadrature with one another, said third and fourth gating signals being in phase quadrature with one another and being phase coherent with said first and second gating signals; a first gate circuit for selectively passing said first input signal in accordance with said third gating signal; a second gate circuit for selectively passing said second input signal in accordance with said fourth gating signal; means coupled to said first and second gate circuits for developing from the output signals from said gate circuits a first informational signal at said second frequency and having an amplitude proportional to said sum vector magnitude and a phase relative to said third and fourth gating signals indicative of the angle of the input sum vector; means for developing from said first informational signal a fifth gating signal at said first frequency and phase coherent with said first informational signal; a third gate circuit for selectively passing said first informational signal in accordance with said fifth gating signal; means coupled to said third gate circuit for developing from the output signal from said third gate circuit a second informational signal at said first frequency and having an amplitude proportional to said sum vector magnitude and a phase relative to said first and second gating signals indicative of one-half of said input sum vector angle; a fourth gate circuit for selectively passing said second informational signal in accordance with said first gating signal; a fifth gate circuit for selectively passing said second informational signal in accordance with said second gating signal; and first and second filter means respectively coupled to said fourth and fifth gate circuits for developing the respective first and second device output signals.