US3654490A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate circuit with ttl input and complimentary outputs
Assignee: Signetics Corp
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Filing: 1970-06-17
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Granted: 1972-04-04
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Expires: 1990-06-17
Abstract
Abstract A gate circuit having a TTL input characteristic with the input transistor forming in effect two steering diodes driving a phase splitter which has its collector and emitter respectively driving two complementary output transistors. The collectors of the output transistors coupled together form the output terminal of the gate circuit and the emitter of one of the output transistors is coupled to a high voltage supply. This output transistor is also coupled to the phase splitter through an inverting current source.
Inventors
- 👤 David T Kan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:48
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
197 words
A gate circuit having an output terminal switchable between two levels in response to a bi-level input signal on an input terminal said circuit comprising: a pair of complementary output transistors with two terminals of the same type coupled together and to said output terminal, each of said transistors also including input control terminals and second output terminals of the same type, in-phase control signals to said input control terminals driving said two output transistors into simultaneous conductive and non-conductive states respectively; phase splitting means having two output terminals of opposite phase each of such terminals being respectively coupled to one of said input control terminals; inverting current source means series coupled between one of said input control terminals and a corresponding output terminal of said phase splitting means to provide in phase signals at said output control terminals said inverting current source means including a transistor with a resistor connected to an output terminal thereof; and means coupling said phase splitting means to said input terminal for driving said phase splitting means into an opposite phase condition in response to a level change in said input signal, whereby said states of said output transistors are reversed.
Claim 2
Dependent Claim
197 words
A gate circuit having an output terminal switchable between two levels in response to a bi-level input signal on an input terminal said circuit comprising: a pair of complementary output transistors with two terminals of the same type coupled together and to said output terminal, each of said transistors also including input control terminals and second output terminals of the same type, in-phase control signals to said input control terminals driving said two output transistors into simultaneous conductive and non-conductive states respectively; phase splitting means having two output terminals of opposite phase each of such terminals being respectively coupled to one of said input control terminals; inverting current source means series coupled between one of said input control terminals and a corresponding output terminal of said phase splitting means to provide in phase signals at said output control terminals said inverting current source means including a transistor with a resistor connected to an output terminal thereof; and means coupling said phase splitting means to said input terminal for driving said phase splitting means into an opposite phase condition in response to a level change in said input signal, whereby said states of said output transistors are reversed.
Claim 3
Dependent Claim
70 words
A gate circuit as in claim 1 where said driving means includes a transistor with emitter and collector terminals, said emitter terminal being coupled to said input terminal of said circuit, said collector terminal being coupled to said phase splitting means, and the effective base-emitter diode and base-collector diode of said transistor acting as current steering diodes for reversing the phase condition on said output terminals of said phase-splitting means.
Claim 4
Dependent Claim
81 words
A gate circuit as in claim 1 where said transistor of said inverting current source has its base terminal coupled to said phase-splitting means, one output terminal coupled to the control input of said output transistor and to a high voltage supply and the other output terminal coupled to common through said resistor, said resistor essentially determining the constant current produced by said current source, such constant current and said high voltage substantially determining the standby power dissipation of said circuit.
Claim 5
Dependent Claim
37 words
A gate circuit as in claim 1 where one of said output transistors has its second output terminal coupled to a high voltage supply and the other output transistor has its second output terminal coupled to common.
Claim 6
Dependent Claim
250 words
A gate circuit having an output terminal switchable between two levels in response to a bi-level input signal on the input terminal said circuit comprising: a pair of complementary output transistors with their collectors coupled together and to said output terminal and having base input control terminals and emitter terminals the emitter terminal of one transistor being coupled to common and the emitter terminal of one transistor being coupled to common and the emitter terminal of the other to a relatively high voltage supply; phase splitting means including a transistor where the emitter of the transistor is coupled to the base input of said output transistor which has its emitter coupled to common and the collector terminal of said phase splitting transistor is Coupled to the base input terminal of the other output transistor through an inverting current source which is series coupled; said inverting current source including a transistor having a collector terminal coupled to the base input of said output transistor, an emitter terminal coupled to ground through a resistor and a base terminal coupled to the collector of the phase splitting transistor; and diode steering means for driving said phase splitting transistor including a transistor having an emitter terminal coupled to the input terminal and a collector terminal coupled to the base input of the phase splitting transistor said driving transistor providing in effect effective diodes between its base-emitter and base-collector terminals to steer current toward and away from the base input of said phase splitting transistor.
Claim 7
Dependent Claim
250 words
A gate circuit having an output terminal switchable between two levels in response to a bi-level input signal on the input terminal said circuit comprising: a pair of complementary output transistors with their collectors coupled together and to said output terminal and having base input control terminals and emitter terminals the emitter terminal of one transistor being coupled to common and the emitter terminal of one transistor being coupled to common and the emitter terminal of the other to a relatively high voltage supply; phase splitting means including a transistor where the emitter of the transistor is coupled to the base input of said output transistor which has its emitter coupled to common and the collector terminal of said phase splitting transistor is Coupled to the base input terminal of the other output transistor through an inverting current source which is series coupled; said inverting current source including a transistor having a collector terminal coupled to the base input of said output transistor, an emitter terminal coupled to ground through a resistor and a base terminal coupled to the collector of the phase splitting transistor; and diode steering means for driving said phase splitting transistor including a transistor having an emitter terminal coupled to the input terminal and a collector terminal coupled to the base input of the phase splitting transistor said driving transistor providing in effect effective diodes between its base-emitter and base-collector terminals to steer current toward and away from the base input of said phase splitting transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-04 | 1975-10-04 | 1976-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-04 | 1979-10-04 | 1980-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-04 | 1983-10-04 | 1984-04-04 | $7700.00 | Window Closed / Lapsed |