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US3648064A
Expired / Lapsed
US
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Multiple signal level high-speed logic circuit device
Assignee: NTT Inc
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Filing: 1969-06-30
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Granted: 1972-03-07
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Expires: 1989-06-30
Abstract
Abstract A multiple signal level high-speed logic circuit device wherein the logic gates within a block operate under both small- and high-logic signal swings through a direct coupling configuration. The small logic signal swing is supplied from a low-voltage electric source, and the interconnections between the respective blocks are made through voltage-level converting circuits which use PN-junction level shifts.
Inventors
- 👤 Hisakazu Mukai
- 👤 Hideaki Kindo
- 👤 Yoshimasa Sugahara
- 👤 Akinori Yamagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812; H03K19/01825; H03K19/01831; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
286 words
A high-speed logic circuit device having multisignal levels, comprising: A. first, second, third and fourth voltage sources; B. a number of low-level logic circuits each comprising; 1. at least two unit gates each consisting of a number of first transistors connected in a common emitter configuration, the base of at least one of said number of first transistors receiving a respective input signal, the collector of at least one of said number of first transistors providing an output signal, means for connecting the common emitters of said first transistors to said first voltage source, said collector of said at least said one first transistor is connected to said second voltage source through a first resistance; 2. means for connecting the collectors of said number of first transistors in a first unit gate to the bases of respective first transistors in a second unit gate; C. a first voltage-level-converting circuit, comprising; 1. a number of second transistors having commonly connected emitters; 2. means for connecting the base of at least one of said second transistors to receive the output signal of said at least one collector in the second unit gate; 3. an output terminal; 4. means for connecting said output terminal to at least one collector of said second transistors; 5. means for connecting said third voltage source to said commonly connected emitters of said second transistors; 6. means for connecting said collector connected to said output terminal to said fourth voltage source through a second resistance; D. a second voltage-level-converting circuit for receiving the logic level outputs of said first voltage-level-converting circuit; and said second and third voltage sources having a voltage difference greater than the voltage difference between said first and second voltage sources.
Claim 2
Dependent Claim
286 words
A high-speed logic circuit device having multisignal levels, comprising: A. first, second, third and fourth voltage sources; B. a number of low-level logic circuits each comprising; 1. at least two unit gates each consisting of a number of first transistors connected in a common emitter configuration, the base of at least one of said number of first transistors receiving a respective input signal, the collector of at least one of said number of first transistors providing an output signal, means for connecting the common emitters of said first transistors to said first voltage source, said collector of said at least said one first transistor is connected to said second voltage source through a first resistance; 2. means for connecting the collectors of said number of first transistors in a first unit gate to the bases of respective first transistors in a second unit gate; C. a first voltage-level-converting circuit, comprising; 1. a number of second transistors having commonly connected emitters; 2. means for connecting the base of at least one of said second transistors to receive the output signal of said at least one collector in the second unit gate; 3. an output terminal; 4. means for connecting said output terminal to at least one collector of said second transistors; 5. means for connecting said third voltage source to said commonly connected emitters of said second transistors; 6. means for connecting said collector connected to said output terminal to said fourth voltage source through a second resistance; D. a second voltage-level-converting circuit for receiving the logic level outputs of said first voltage-level-converting circuit; and said second and third voltage sources having a voltage difference greater than the voltage difference between said first and second voltage sources.
Claim 3
Dependent Claim
34 words
means for connecting the collectors of said number of first transistors in a first unit gate to the bases of respective first transistors in a second unit gate; C. a first voltage-level-converting circuit, comprising;
Claim 4
Dependent Claim
34 words
means for connecting the collectors of said number of first transistors in a first unit gate to the bases of respective first transistors in a second unit gate; C. a first voltage-level-converting circuit, comprising;
Claim 5
Dependent Claim
29 words
means for connecting the base of at least one of said second transistors to receive the output signal of said at least one collector in the second unit gate;
Claim 6
Dependent Claim
29 words
means for connecting the base of at least one of said second transistors to receive the output signal of said at least one collector in the second unit gate;
Claim 7
Dependent Claim
49 words
A high-speed logic circuit device as in claim 1 further comprising a voltage source having an output voltage that varies similarly with temperature as the forward voltage of said first transistors in said low level logic circuits and is used as an electric source for said low-level logic circuit.
Claim 8
Dependent Claim
77 words
A high-speed logic circuit Device as in claim 1 wherein said first voltage-level-converting circuit further includes at least one PN-junction in said means for connecting said output signal of said low-level logic circuit to the base of at least one of said second transistors, and a second PN-junction connected to the base of another of said second transistors to supply a constant voltage level from the intermediate level of binary logic signals in said low-level logic circuits.
Claim 9
Dependent Claim
3 words
an output terminal;
Claim 10
Dependent Claim
3 words
an output terminal;
Claim 11
Dependent Claim
15 words
means for connecting said output terminal to at least one collector of said second transistors;
Claim 12
Dependent Claim
15 words
means for connecting said output terminal to at least one collector of said second transistors;
Claim 13
Dependent Claim
68 words
A high-speed logic circuit device as in claim 8 further comprising a high-level logic gate connected between said first voltage converting circuit and said second voltage converting circuit, said gate comprising; a number of third transistors, and at least one PN-junction for shifting the signal level between two of said third transistors whereby said high-level logic gate operates with a greater logic swing than said low-level logic gates.
Claim 14
Dependent Claim
38 words
A high-speed logic circuit device as in claim 4 wherein said high-level logic gate has an output terminal connected to a transmission line and a third resistance is connected between said first voltage source and said transmission line.
Claim 15
Dependent Claim
16 words
means for connecting said third voltage source to said commonly connected emitters of said second transistors;
Claim 16
Dependent Claim
16 words
means for connecting said third voltage source to said commonly connected emitters of said second transistors;
Claim 17
Dependent Claim
58 words
means for connecting said collector connected to said output terminal to said fourth voltage source through a second resistance; D. a second voltage-level-converting circuit for receiving the logic level outputs of said first voltage-level-converting circuit; and said second and third voltage sources having a voltage difference greater than the voltage difference between said first and second voltage sources.
Claim 18
Dependent Claim
58 words
means for connecting said collector connected to said output terminal to said fourth voltage source through a second resistance; D. a second voltage-level-converting circuit for receiving the logic level outputs of said first voltage-level-converting circuit; and said second and third voltage sources having a voltage difference greater than the voltage difference between said first and second voltage sources.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |