Patent US3638304A successfully refreshed from Google Patents.
US3638304A
Expired / Lapsed
US
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Semiconductive chip attachment method
Assignee: Motors Liquidation Co
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Filing: 1969-11-06
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Granted: 1972-02-01
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Expires: 1989-11-06
Abstract
Abstract A method for mounting a semiconductive chip on a substrate, using integral leads, and a method for making the leads. The techniques described are particularly useful in making integral leads on a semiconductive chip which can be flipped onto a complementary conductor network. The leads are preferably formed on the chip while the chip is still part of a slice. The leads are simultaneously formed on the slice by progressive solidification from a melt material, and the slice subsequently diced to form the individual leaded chips.
Inventors
- 👤 Carl E Bleil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:08
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/20; H10W72/251; H10W72/252; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
166 words
The method of mounting a semiconductive chip on a substrate having a circuit pattern with contact regions conforming to contact regions on said chip, said method comprising the steps of masking the surface of one of said chips and said substrate except for said contact regions, placing the masked surface in contact with a melt of a metal melting at a temperature above the chip bonding temperature and below the melting temperature of said chip and substrate materials, removing heat from said surface while it is in contact with said melt to progressively solidify melt metal onto said contact regions, concurrently slowly withdrawing said element from said melt at a rate commensurate with said progressive solidification to form solid contact spires of predetermined height on said contact regions, registering said contact spires with the contact regions on the other element and bonding the registered portions together while maintaining the integrity of the contact spires to maintain the bonded chip and substrate elements in mutually spaced relationship.
Claim 2
Independent Claim
166 words
The method of mounting a semiconductive chip on a substrate having a circuit pattern with contact regions conforming to contact regions on said chip, said method comprising the steps of masking the surface of one of said chips and said substrate except for said contact regions, placing the masked surface in contact with a melt of a metal melting at a temperature above the chip bonding temperature and below the melting temperature of said chip and substrate materials, removing heat from said surface while it is in contact with said melt to progressively solidify melt metal onto said contact regions, concurrently slowly withdrawing said element from said melt at a rate commensurate with said progressive solidification to form solid contact spires of predetermined height on said contact regions, registering said contact spires with the contact regions on the other element and bonding the registered portions together while maintaining the integrity of the contact spires to maintain the bonded chip and substrate elements in mutually spaced relationship.
Claim 3
Dependent Claim
24 words
The method as defined in claim 1 wherein the semiconductive chip is of a semiconductor selected from the group consisting of germanium and silicon.
Claim 4
Independent Claim
208 words
The method of forming integral contact leads on a semiconductive chip and bonding said chip to a complementary supportiNg substrate having conductors comprising the steps of forming a plurality of discrete electronic device regions on a semiconductor slice, forming a plurality of electrodes on the surface of said slice for each discrete device region, forming a spire base layer on at least a portion of each of said electrodes, masking the balance of said surface and said electrode, placing said masked surface in contact with a melt of spire metal, cooling said slice while slowly withdrawing it from said melt to progressively solidify melt metal as extended sprires of predetermined height on said base layer, said melt metal having a melting point below that of the semiconductive material and above the temperature at which it is to be bonded to a substrate, dicing the slice to produce a plurality of chips, each of which contain a discrete electronic device region, placing said chip on a substrate having a conductor pattern including metal coated regions for registration with said chip spires, contacting said metal coated regions with the tips of said spires, and bonding said spires to said regions to connect said chip to the conductors of said substrate.
Claim 5
Independent Claim
208 words
The method of forming integral contact leads on a semiconductive chip and bonding said chip to a complementary supportiNg substrate having conductors comprising the steps of forming a plurality of discrete electronic device regions on a semiconductor slice, forming a plurality of electrodes on the surface of said slice for each discrete device region, forming a spire base layer on at least a portion of each of said electrodes, masking the balance of said surface and said electrode, placing said masked surface in contact with a melt of spire metal, cooling said slice while slowly withdrawing it from said melt to progressively solidify melt metal as extended sprires of predetermined height on said base layer, said melt metal having a melting point below that of the semiconductive material and above the temperature at which it is to be bonded to a substrate, dicing the slice to produce a plurality of chips, each of which contain a discrete electronic device region, placing said chip on a substrate having a conductor pattern including metal coated regions for registration with said chip spires, contacting said metal coated regions with the tips of said spires, and bonding said spires to said regions to connect said chip to the conductors of said substrate.
Claim 6
Dependent Claim
61 words
The method as defined in claim 3 wherein the semiconductor is selected from the group consisting of germanium and silicon, the metal coating on the substrate is a solder, the solder melts at a temperature below that at which the spires melt, and the thickness of the solder coating is greater than the maximum deviation in spire height on the chip.
Claim 7
Dependent Claim
27 words
The method as defined in claim 3 in which the chip spires are ground to uniform height before the chip is placed in contact with the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-31 | 1975-08-02 | 1976-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-31 | 1979-08-02 | 1980-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-31 | 1983-08-02 | 1984-02-01 | $7700.00 | Window Closed / Lapsed |