Ttl input array with bypass diode

Claim 2

In a logic gate, a. a transistor having base and collector terminals and at least one emitter terminal, b. a source of DC potential, c. a biasing resistor having first and second terminals, said first terminal being connected to said source of DC potential, d. first means having first and second terminals for controlling the bias at said collector terminal, said first terminal of said first means being connected to said second terminal of said resistor, and said second terminal of said first means being connected to said collector terminal wherein said first means includes a diode, e. second means having first and second terminals for applying bias signals at said base terminal, said first terminal of said second means being connected to said second terminal of said resistor, and said second terminal of said second means being connected to said base terminal, and f. third means having first and second terminals for bypassing a portion of said bias signals at said base terminal, said first terminal of said third means being connected to said base terminal, and said second terminal of said third means being connected to said collector terminal.

Claim 3

A circuit as in claim 1 wherein said diode is a diode-connected transistor having material, manufacturing process and temperature characteristics substantially identical to those of said transistor.

Claim 4

In combination in a transistor logic gate a. a first multiemitter transistor, b. a source of DC potential, c. a point of reference potential, d. first and second series-connected resistors coupling said source of DC potential to the base of said first multiemitter transistor, e. a first diode connected between the junction of said first and second resistors and the collector of said first multiemitter transistor, f. a third resistor connected between the base and collector of said first multiemitter transistor, g. a second multiemitter transistor, h. a fourth resistor connecting said source of DC potential to the collector of said second multiemitter transistor, i. means connecting the base of said second multiemitter transistor to the collector of said first multiemitter transistor, j. means connecting one emitter of said second multiemitter transistor to the base of said second multiemitter transistor, k. means connecting a second emitter of said second multiemitter transistor to said point of reference potential, and l. a network comprising a diode and a resistor connected in series, said network being connected between the collector of said second multiemitter transistor and said point of reference potential, said network being arranged to control the voltage at said collector of said second multiemitter transistor.

Claim 5

In combination in a transistor logic gate a. a first multiemitter transistor, b. a source of DC potential, c. a point of reference potential, d. first and second series-connected resistors coupling said source of DC potential to the base of said first multiemitter transistor, e. a first diode connected between the junction of said first and second resistors and the collector of said first multiemitter transistor, f. a third resistor connected between the base and collector of said first multiemitter transistor, g. a second multiemitter transistor, h. a fourth resistor connecting said source of DC potential to the collector of said second multiemitter transistor, i. means connecting the base of said second multiemitter transistor to the collector of said first multiemitter transistor, j. means connecting one emitter of said second multiemitter transistor to the base of said second multiemitter transistor, k. means connecting a second emitter of said second multiemitter transistor to said point of reference potential, and l. a network comprising a diode and a resistor connected in series, said network being connected between the collector of said second multiemitter transistor and said point of reference potential, said network being arranged to control the voltage at said collector of said second multiemitter transistor.

Claim 6

In a logic gate responsive to a plurality of sources of logic signals, a. a transistor having base and collector terminals and a plurality of emitter terminals, b. said plurality of soUrces of logic signals each arranged to apply logic signals to a corresponding one of said emitter terminals, c. a source of DC potential, d. a bias resistor having first and second terminals, said first terminal being connected to said source of DC potential, and e. first means including a diode saturable in response to high-level signals on all of said emitter terminals, for controllably applying bias signals from said second terminal of said bias resistor to said base and collector terminals, thereby limiting undesired inverse internal currents from said collector terminal to one or more of said emitter terminals while maintaining the logic threshold at each of said emitter terminals at a satisfactory level.

Claim 7

In a logic gate responsive to a plurality of sources of logic signals, a. a transistor having base and collector terminals and a plurality of emitter terminals, b. said plurality of soUrces of logic signals each arranged to apply logic signals to a corresponding one of said emitter terminals, c. a source of DC potential, d. a bias resistor having first and second terminals, said first terminal being connected to said source of DC potential, and e. first means including a diode saturable in response to high-level signals on all of said emitter terminals, for controllably applying bias signals from said second terminal of said bias resistor to said base and collector terminals, thereby limiting undesired inverse internal currents from said collector terminal to one or more of said emitter terminals while maintaining the logic threshold at each of said emitter terminals at a satisfactory level.

Claim 8

Apparatus as in claim 4 wherein said first means clamping further comprises a voltage divider for applying across said base and collector terminals a portion of the voltage drop across said diode.