Patent US3628069A successfully refreshed from Google Patents.
US3628069A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit having monolithic inversely operated transistors
Assignee: International Business Machines Corp
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Filing: 1969-04-29
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Granted: 1971-12-14
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Expires: 1989-04-29
Abstract
Abstract A planar monolithic circuit is made with a plurality of transistors in a single isolated region in a common emitter circuit configuration. An N-type epitaxial layer constitutes the emitter region into which the base regions of a P-type material are subsequently diffused, and an N-type collector is then diffused into the base regions forming NPN transistors. The Ntype epitaxial region can simultaneously be the common collector region for some of the transistors and the common emitter region for other ones of the transistor in an operative circuit arrangement. Three transistors in a single isolated region can be formed in the shape of an ''''L'''' so that when two of these are interlinked, a rectangle is formed.
Inventors
- 👤 Knut K Najmann
- 👤 Hermann Frantz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/085; Y10S148/151
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
125 words
A planar monolithic circuit having a plurality of transistors in each of two isolated regions comprising: two isolated regions; at least two transistors, in the first isolated region having an epitaxial layer as a common emitter region; cross-coupling conductors between said two transistors in said first isolated region, forming a bistable circuit; a plurality of transistors in the second isolated region forming a control and sensing circuit for said bistable circuit at least one of said plurality of transistors in said second region having a collector region the same as an emitter region of at least another one of the said plurality of transistors in said second region; and connecting means for establishing electrical contact between said bistable circuit and said control and sensing circuit.
Claim 2
Dependent Claim
125 words
A planar monolithic circuit having a plurality of transistors in each of two isolated regions comprising: two isolated regions; at least two transistors, in the first isolated region having an epitaxial layer as a common emitter region; cross-coupling conductors between said two transistors in said first isolated region, forming a bistable circuit; a plurality of transistors in the second isolated region forming a control and sensing circuit for said bistable circuit at least one of said plurality of transistors in said second region having a collector region the same as an emitter region of at least another one of the said plurality of transistors in said second region; and connecting means for establishing electrical contact between said bistable circuit and said control and sensing circuit.
Claim 3
Dependent Claim
162 words
A planar monolithic circuit having a plurality of transistors in each of a plurality of isolated regions comprising: a first one of said plurality of isolated regions having two cross-coupled transistors in a common emitter configuration, forming a multivibrator; a second one of said plurality of isolated regions having three transistors such that said epitaxial layer is the common emitter for two of the said transistors and the collector for the third of the said transistors; at least two conductive paths for connecting the two transistors in the first one of said plurality of isolated regions with at least two of the three transistors in said second one of said plurality of isolated regions; whereby the two transistors in said first one of said plurality of isolated regions form a multivibrator and the three transistors in said second one of said plurality of isolated regions form a differential amplifier together with an addressable gate transistor, said combination providing an operational storage cell.
Claim 4
Dependent Claim
162 words
A planar monolithic circuit having a plurality of transistors in each of a plurality of isolated regions comprising: a first one of said plurality of isolated regions having two cross-coupled transistors in a common emitter configuration, forming a multivibrator; a second one of said plurality of isolated regions having three transistors such that said epitaxial layer is the common emitter for two of the said transistors and the collector for the third of the said transistors; at least two conductive paths for connecting the two transistors in the first one of said plurality of isolated regions with at least two of the three transistors in said second one of said plurality of isolated regions; whereby the two transistors in said first one of said plurality of isolated regions form a multivibrator and the three transistors in said second one of said plurality of isolated regions form a differential amplifier together with an addressable gate transistor, said combination providing an operational storage cell.
Claim 5
Dependent Claim
36 words
A monolithic storage matrix in accordance with the circuit of claim 2 wherein said second one of said plurality of isolated regions is ''''L''''-shaped and pairs of said ''''L''''-shaped isolated regions are interlinked, forming a rectangle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-13 | 1975-06-14 | 1975-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-13 | 1979-06-14 | 1979-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-13 | 1983-06-14 | 1983-12-14 | $7700.00 | Window Closed / Lapsed |