High-speed divider utilizing carry save additions

Claim 2

A high-speed divider for performing a division operation between a dividend signal and a divisor signal comprising: first register means including a first and a second register for holding sum and carry signal representative of a partial remainder, respectively, means for initially supplying said dividend signal and a zero signal as the sum and carry signals in said first and second registers, respectively; decoder means for calculating a round figure of the partial remainder from the upper parts of predetermined figures of sum and carry signals held in said first and second registers, thereby producing a partial quotient consisting of either of three different signals indicating 1, 0, and -1; selecting means for selectively producing either one of three different signals in the form of the divisor signal, zero and the complement of the divisor signal in response to the three different signals from said decoder means indicating -1, 0 and 1, respectively; shifting means for shifting upwards the sum and carry signals held in the first and second registers by one figure, including holding means for holding the shifted sum and carry signals, respectively; carry save adder means for adding the shifted sum and carry signals supplied from said shifting and holding means with the selected signal supplied from said selecting means to produce new sum and carry signals representative of a new partial remainder, and operatively replacing the partial remainder previously held in the first register means with the new partial remainder so that said first register means, decoder means, selecting means, shifting and holding means and carry save adder means may repeat their operations in accordance with subsequently renewed partial remainders; and second register means for holding partial quotients sequentially obtained from said decoder means thereby obtaining a quotient from the sequentially held partial quotients.

Claim 3

A high-speed divider according to claim 1, wherein said second register means comprises means for holding in succession the sequence of occurrences of such partial quotient indicating 1 and means for holding in succession the sequence of occurrences of such partial quotient indicating -1.

Claim 4

A high-speed divider for performing a division operation between a dividend signal and a divisor signal comprising: first register means including a first and a second register for holding sum and carry signals representative of a partial remainder, respectively; means for initially supplying said dividend signal and a zero signal as sum and carry signals in the first and second registers, respectively; decoder means for producing a partial quotient consisting of a plurality of figures, each figure of the partial quotient consisting of either of three different signals indicating 1, 0 and -1 in response to both the upper parts of predetermined figures of sum and carry signals representative of a partial remainder held in said first and second regiSters and the upper parts of predetermined figures of said divisor; selecting means having a plurality of gate means provided to correspond to respective figures of the partial quotient, each selectively producing either one of three different signals in the form of the divisor signal, zero and complement of the divisor signal in response to the indications of -1, 0 and 1 of the corresponding figure of partial quotient, respectively, from said decoder means; shifting means for shifting upwards the sum and carry signals held in the first and second registers by the same number of figures as that of the figures of the partial quotient, including holding means for holding the shifted sum and carry signals, respectively; a plurality of carry save adders of the same number as that of the figures of the partial quotient connected in cascade and provided to correspond to said gate means, one of which operatingly adds the shifted sum and carry signals supplied from said shifting and holding means with a selected signal supplied from said gate means corresponding to the higher figure of the partial quotient to produce new sum and carry signals and the other of which operatingly adds said new sum and carry signals supplied from the first mentioned one of the adders with a selected signal supplied from said gate means corresponding to the lower figure of the partial quotient to produce the other new sum and carry signals representative of a new partial remainder and operatively replaces the previous partial remainder in the first register means with the new partial remainder, so that said first register means, decoder means, selecting means, shifting and holding means and plural carry save adders may repeat their operations in accordance with subsequently renewed partial remainder; and second register means for holding partial quotients sequentially obtained from said decoder means; thereby obtaining a quotient from the sequentially held partial quotients.

Claim 5

A high-speed divider for performing a division operation between a dividend signal and a divisor signal comprising: first register means including a first and a second register for holding sum and carry signals representative of a partial remainder, respectively; means for initially supplying said dividend signal and a zero signal as sum and carry signals in the first and second registers, respectively; decoder means for producing a partial quotient consisting of a plurality of figures, each figure of the partial quotient consisting of either of three different signals indicating 1, 0 and -1 in response to both the upper parts of predetermined figures of sum and carry signals representative of a partial remainder held in said first and second regiSters and the upper parts of predetermined figures of said divisor; selecting means having a plurality of gate means provided to correspond to respective figures of the partial quotient, each selectively producing either one of three different signals in the form of the divisor signal, zero and complement of the divisor signal in response to the indications of -1, 0 and 1 of the corresponding figure of partial quotient, respectively, from said decoder means; shifting means for shifting upwards the sum and carry signals held in the first and second registers by the same number of figures as that of the figures of the partial quotient, including holding means for holding the shifted sum and carry signals, respectively; a plurality of carry save adders of the same number as that of the figures of the partial quotient connected in cascade and provided to correspond to said gate means, one of which operatingly adds the shifted sum and carry signals supplied from said shifting and holding means with a selected signal supplied from said gate means corresponding to the higher figure of the partial quotient to produce new sum and carry signals and the other of which operatingly adds said new sum and carry signals supplied from the first mentioned one of the adders with a selected signal supplied from said gate means corresponding to the lower figure of the partial quotient to produce the other new sum and carry signals representative of a new partial remainder and operatively replaces the previous partial remainder in the first register means with the new partial remainder, so that said first register means, decoder means, selecting means, shifting and holding means and plural carry save adders may repeat their operations in accordance with subsequently renewed partial remainder; and second register means for holding partial quotients sequentially obtained from said decoder means; thereby obtaining a quotient from the sequentially held partial quotients.

Claim 6

A high-speed divider according to claim 3, wherein said decoder means comprises means connected to said first and second registers for adding the upper parts of said sum and carry signals to each other and means for generating a partial quotient of at least two figures from the output of said adding means and upper part of predetermined figures of said divisor.