Full adder employing exclusive-nor circuitry

Claim 2

A fuller adder stage responsive to correspondingly ordered addend and augend signals applied to said stage and to a carry signal applied thereto from the next-lower-ordered stage for generating sum and carry signals, said stage comprising; first circuit means comprising, first, second, third and fourth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying said addend signals to the base electRodes of said second and third transistors, means for applying said augend signals to the base electrodes of said first and fourth transistors, means for rendering nonconductive said second and fourth transistors upon respective conduction of said first and third transistors to the base electrodes of said second and fourth transistors, and means connecting the collector electrodes of said second and fourth transistors together and to a source of potential whereby there is provided at the collector electrodes of said second and fourth transistors an output signal that is representative of the exclusive-NOR function of said addend and augend signals; second circuit means responsive to said lower-ordered-stage carry signal and to said exclusive-NOR function signal for generating a sum signal; and third circuit means responsive to one of said addend and augend signals, to said lower-ordered-stage carry signal and to said exclusive-NOR function signal for generating a carry signal.

Claim 3

A stage as in claim 1 wherein said second circuit means comprises first, second, third and fourth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying the output signal from said first circuit means to the base electrodes of said second and third transistors, means for applying said lower-ordered-stage carry signal to the base electrodes of said first and fourth transistors, means for rendering nonconductive said second and fourth transistors upon respective conduction of said first and third transistors, comprising means respectively connecting the collector electrodes of said first and third transistors to the base electrodes of said second and fourth transistors, and means connecting the collector electrodes of said second and fourth transistors together and to said source of potential whereby there is provided at the collector electrodes of said second and fourth transistors an output signal that is representative of the sum signal of said addend, augend and lower-ordered-stage carry signals.

Claim 4

A full adder stage responsive to correspondingly ordered addend and augend signals applied to said stage and to carry signal applied thereto from the next-lower-ordered stage for generating sum and carry signals, said stage comprising; first circuit means comprising, first, second, third and fourth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying said addend signals to the base electrodes of said second and third transistors, means for applying said augend signals to the base electrodes of said first and fourth transistors, means respectively connecting the collector electrodes of said first and third transistors to the base electrodes of said second and fourth transistors, and means connecting the collector electrodes of said second and fourth transistors together and to a source of potential whereby there is provided at the collector electrodes of said second and fourth transistors an output signal that is representative of the exclusive-NOR function of said addend and augend signals; second circuit means comprising, first, second, third and fourth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying the output signal from said first circuit means to be base electrodes of said second and third transistors, means for applying said lower-ordered-stage carry signal to the base electrodes of said first and fourth transistors, means respectively connecting the collector electrodes of said first and third transistors to the base electrodes of said second and fourth transistors, and means connecting the collector electrodes of said second and fourth transistors together and to said source of potential whereby there is provided at the collector electrodes of said second and fourth transistors an output signal that is representative of the sum signal of said addend, augend and lower-ordered-stage carry signals; and third circuit means comprising, first, second, third, fourth and fifth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying the output signal from said first circuit means to the base electrodes of said second and third transistors, means for applying one of said addend and augend signals to the base electrode of said first transistor, means for applying said lower-ordered-stage carry signal to the base electrode of said fourth transistor, means connecting the collector electrodes of said third and fourth transistors and the base electrode of said fifth transistor together and to said source of potential, means connecting the collector electrode of said first transistor to the base electrode of said second transistor, and means connecting the collector electrodes of said second and fifth transistors together and to said source of potential whereby there is provided at the collector electrodes of said second and fifth transistors an output signal that is representative of the carry signal of said addend, augend and lower-ordered-stage carry signals.

Claim 5

A full adder stage responsive to correspondingly ordered addend and augend signals applied to said stage and to carry signal applied thereto from the next-lower-ordered stage for generating sum and carry signals, said stage comprising; first circuit means comprising, first, second, third and fourth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying said addend signals to the base electrodes of said second and third transistors, means for applying said augend signals to the base electrodes of said first and fourth transistors, means respectively connecting the collector electrodes of said first and third transistors to the base electrodes of said second and fourth transistors, and means connecting the collector electrodes of said second and fourth transistors together and to a source of potential whereby there is provided at the collector electrodes of said second and fourth transistors an output signal that is representative of the exclusive-NOR function of said addend and augend signals; second circuit means comprising, first, second, third and fourth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying the output signal from said first circuit means to be base electrodes of said second and third transistors, means for applying said lower-ordered-stage carry signal to the base electrodes of said first and fourth transistors, means respectively connecting the collector electrodes of said first and third transistors to the base electrodes of said second and fourth transistors, and means connecting the collector electrodes of said second and fourth transistors together and to said source of potential whereby there is provided at the collector electrodes of said second and fourth transistors an output signal that is representative of the sum signal of said addend, augend and lower-ordered-stage carry signals; and third circuit means comprising, first, second, third, fourth and fifth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying the output signal from said first circuit means to the base electrodes of said second and third transistors, means for applying one of said addend and augend signals to the base electrode of said first transistor, means for applying said lower-ordered-stage carry signal to the base electrode of said fourth transistor, means connecting the collector electrodes of said third and fourth transistors and the base electrode of said fifth transistor together and to said source of potential, means connecting the collector electrode of said first transistor to the base electrode of said second transistor, and means connecting the collector electrodes of said second and fifth transistors together and to said source of potential whereby there is provided at the collector electrodes of said second and fifth transistors an output signal that is representative of the carry signal of said addend, augend and lower-ordered-stage carry signals.

Claim 6

A full adder stage responsive to correspondingly ordered addend and augend signals applied to said stage and to a carry signal applied thereto from the next-lower-ordered stage for generating sum and carry signals, said stage comprising; first circuit means responsive to said addend and augend signals for generating a signal representative of the exclusive-NOR function of said addend and augend signals; second circuit means responsive to said lower-ordered-stage carry signal and to said exclusive-NOR function signal for generating a sum signal, and third circuit means comprising, first, second, third, fourth and fifth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying the output signal from said first circuit means to the base electrodes of said second and third transistors, means for applying one of said addend and augend signals to the base electrode of said first transistor, means for applying said lower-ordered-stage carry signal to the base electrode of said fourth transistor, means connecting the collector electrodes of said third and fourth transistors and the base electrode of said fifth transistor together and to a source of potential, means connecting the collector electrode of said first transistor to the base electrode of said second transistor, and means connecting the collector electrodes of said second and fifth transistors together and to said source of potential whereby there is provided at the collector electrodes of said second and fifth transistors an output signal that is representative of the carry signal of said addend, augend and lower-ordered-stage carry signals.

Claim 7

A full adder stage responsive to correspondingly ordered addend and augend signals applied to said stage and to a carry signal applied thereto from the next-lower-ordered stage for generating sum and carry signals, said stage comprising; first circuit means responsive to said addend and augend signals for generating a signal representative of the exclusive-NOR function of said addend and augend signals; second circuit means responsive to said lower-ordered-stage carry signal and to said exclusive-NOR function signal for generating a sum signal, and third circuit means comprising, first, second, third, fourth and fifth transistors each having base, emitter and collector electrodes, means connecting the emitter electrodes of said transistors to a point of reference potential, means for applying the output signal from said first circuit means to the base electrodes of said second and third transistors, means for applying one of said addend and augend signals to the base electrode of said first transistor, means for applying said lower-ordered-stage carry signal to the base electrode of said fourth transistor, means connecting the collector electrodes of said third and fourth transistors and the base electrode of said fifth transistor together and to a source of potential, means connecting the collector electrode of said first transistor to the base electrode of said second transistor, and means connecting the collector electrodes of said second and fifth transistors together and to said source of potential whereby there is provided at the collector electrodes of said second and fifth transistors an output signal that is representative of the carry signal of said addend, augend and lower-ordered-stage carry signals.

Claim 8

A logic circuit comprising a series of n stages, where n is a number greater than 2, each having first and second inputs and an output; each of said stages having means for generating a signal at said output representative of the exclusive-NOR function of signals applied to said first and second inputs; n+1 input signal terminals; means individually connecting said first inputs of said stages to respective ones of said n+1 input signal terminals; means connecting said second input of the first stage of said series to the remaining one of said input signal terminals; and means connecting said second input of each of the remaining sTages of said series to said output of the previous stage; whereby a signal is provided at the output of the last stage of said series representative of the exclusive-OR function of signals applied to said input terminals if n is even, and representative of the exclusive-NOR function of said input terminal signals if n is odd.

Claim 9

A logic circuit comprising a series of n stages, where n is a number greater than 2, each having first and second inputs and an output; each of said stages having means for generating a signal at said output representative of the exclusive-NOR function of signals applied to said first and second inputs; n+1 input signal terminals; means individually connecting said first inputs of said stages to respective ones of said n+1 input signal terminals; means connecting said second input of the first stage of said series to the remaining one of said input signal terminals; and means connecting said second input of each of the remaining sTages of said series to said output of the previous stage; whereby a signal is provided at the output of the last stage of said series representative of the exclusive-OR function of signals applied to said input terminals if n is even, and representative of the exclusive-NOR function of said input terminal signals if n is odd.