Nonlinear encoder

Claim 2

A nonlinear encoder comprising a plurality of circuit stages connected in cascade, each of said circuit stages having input and output characteristics expressed in terms of a horizontal coordinate axis representing input signals and a vertical coordinate axis representing output signals as a plurality of nonoverlapping continuous straight line segments extending between a minimum level and a maximum level of an output signal and each of said circuit stages producing code output signals corresponding to the levels of said input signals, the characteristic of one of said circuit stages having a number of nonoverlapping continuous straight line segments and the characteristic of a succeeding one of said circuit stages having a lesser number of nonoverlapping continuous straight line segments, at least one of said circuit stages comprising analog signal input means for providing an input signal, a plurality of PCM code output circuits connected to said signal input means each having a predetermined reference threshold level different from that of the others for comparing the reference threshold level with the level of the input signal and providing the comparison results as PCM signals, delay means connected to said signal input means for delaying the input signal, a plurality of bias circuits each adding a different bias voltage to the output of the delay means, a plurality of switching means for applying bias voltages to the input signal in accordance with the output signals of the PCM code output circuits, a plurality of amplifier means for amplifying the output signals to which a bias voltage is applied, adding means connected to said amplifier means for adding the outputs of said amplifier means and output means connected to the adding means for providing an output signal.

Claim 3

A nonlinear encoder as claimed in claim 1, wherein the first of said circuit stages comprises a circuit arrangement for determining the polarity of the input signal.

Claim 4

A nonlinear encoder as claimed in claim 2, wherein one of said circuit stages comprises a quaternary circuit arrangement and another of said circuit stages succeeding said one of said circuit stages comprises a binary circuit arrangement.

Claim 5

A nonlinear encoder as claimed in claim 3, wherein the second of said circuit stages comprises a quaternary circuit and the third of said circuit stages comprises a binary circuit arrangement.

Claim 6

A nonlinear encoder as claimed in claim 4, wherein the first of said circuit stages comprises a PCM code output circuit, rectifier means, input means for supplying an input signal to said PCM code input circuit and said rectifier means, a bias circuit connected to said rectifier means for adding a bias voltage to the output of said rEctifier means, and amplifier means connected to said bias circuit for amplifying the biased voltage.

Claim 7

A nonlinear encoder as claimed in claim 4, wherein the second of said circuit stages comprises a plurality of PCM code output circuits having different comparison levels, delay means, input means for supplying an input signal to said PCM code output circuits and to said delay means in common, a plurality of bias circuits each adding a different bias voltage to the output of said delay means, a plurality of amplifier means each connected in series circuit arrangement with a corresponding one of said bias circuits and each providing a different amplification, adding means connected in common to said amplifier means, a plurality of sources of voltage, and a plurality of switching means controlled in operation by said PCM code output circuits, each selectively connecting a corresponding one of said series circuit arrangements to said delay means and each selectively connecting a corresponding one of said series circuit arrangements to a corresponding source of voltage.

Claim 8

A nonlinear encoder as claimed in claim 4, wherein the third of said circuit stages comprises a PCM code output circuit, delay means, input means for supplying an input signal to said PCM code output circuit and to said delay means, a pair of bias circuits each adding a different bias voltage to the output of said delay means, a pair of amplifier means each connected in series circuit arrangement with a corresponding one of said bias circuits and each providing a different amplification, adding means connected in common to said amplifier means, a pair of sources of voltage, and a pair of switching means each controlled in operation by said PCM code output circuit, each selectively connecting a corresponding one of said series circuit arrangements to said delay means and each selectively connecting a corresponding one of said series circuit arrangements to a corresponding source of voltage.

Claim 9

A nonlinear encoder as claimed in claim 5, wherein the second of said circuit stages comprises a plurality of PCM code output circuits having different comparison levels, delay means, input means for supplying an input signal to said PCM code output circuits and to said delay means in common, a plurality of bias circuits each adding a different bias voltage to the output of said delay means, a plurality of amplifier means each connected in series circuit arrangement with a corresponding one of said bias circuits and each providing a different amplification, adding means connected in common to said amplifier means, a plurality of sources of voltage, and a plurality of switching means controlled in operation by said PCM code output circuits, each selectively connecting a corresponding one of said series circuit arrangements to said delay means and each selectively connecting a corresponding one of said series circuit arrangements to a corresponding source of voltage, and wherein the third of said circuit stages comprises a PCM code output circuit, delay means, input means for supplying an input signal to said PCM code output circuit and to said delay means, a pair of bias circuits each adding a different bias voltage to the output of said delay means, a pair of amplifier means each connected in series circuit arrangement with a corresponding one of said bias circuits and each providing a different amplification, adding means connected in common to said amplifier means, a pair of sources of voltage, and a pair of switching means each controlled in operation by said PCM code output circuit, each selectively connecting a corresponding one of said series circuit arrangements to said delay means and each selectively connecting a corresponding one of said series circuit arrangements to a corresponding source of voltage.