US3447146A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Quaternary encoding using multiple feedback loops around operational amplifiers
Assignee: AT&T Inc
•
Filing: 1965-12-29
•
Granted: 1969-05-27
•
Expires: 1985-12-29
Abstract
No abstract record available.
Inventors
- 👤 Veikko R Saari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:42
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/22
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
364 words
AN ENCODING STAGE FOR A STAGE-BY-STAGE ENCODER WHICH COMPRISES, IN COMBINATION, AN AMPLIFIER HAVING AN INPUT TERMINAL AND AN OUTPUT TERMINAL, A SIGNAL INPUT TERMINAL CONNECTED TO SAID AMPLIFIER INPUT TERMINAL, A DIGIT OUTPUT TERMINAL AT WHICH A FIRST DIGIT OUTPUT SIGNAL IS OBTAINED CONNECTED TO SAID AMPLIFIER OUTPUT TERMINALS, TWO DIODES, A FIRST OF SAID DIODES HAVING ITS CATHODE CONNECTED TO THE OUTPUT TERMINAL OF SAID AMPLIFIER AND THE SECOND OF SAID DIODES HAVING ITS ANODE CONNECTED TO THE OUTPUT TERMINAL OF SAID AMPLIFIER, FIRST AND SECOND FEEDBACK PATHS CONNECTED BETWEEN SAID AMPLIFIER INPUT TERMINAL AND THE ANODE OF SAID FIRST DIODE, EACH OF SAID FEEDBACK PATHS COMPRISING THE SERIES COMBINATION OF A DIODE AND A RESISTANCE WITH THE CATHODE IN THE FIRST PATH POLED TO CONDUCT CURRENT IN THE OPPOSITE DIRECTION FROM THE DIODE IN SAID SECOND PATH, THIRD AND FOURTH FEEDBACK PATHS EACH COMPRISING THE SERIES COMBINATION OF A DIODE AND A RESISTANCE CONNECTED BETWEEN SAID AMPLIFIER INPUT TERMINAL AND THE CATHODE OF SAID DIODE WHOSE ANODE IS CONNECTED TO THE AMPLIFIER OUTPUT TERMINAL, THE DIODE IN SAID THIRD FEEDBACK PATH BEING POLED TO CONDUCT CURRENT IN THE OPPOSITE DIRECTION FROM THE DIODE IN SAID FOURTH FEEDBACK PATH, MEANS FOR DERIVING A FIRST ANALOG CURRENT SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE OF SAID FIRST FEEDBACK PATH, MEANS FOR DERIVING A SECOND ANALOG SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE OF SAID SECOND PATH, MEANS FOR DERIVING A THIRD ANALOG SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE OF SAID THIRD PATH, MEANS FOR DERIVING A FOURTH ANALOG SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE IN SAID FOURTH FEEDBACK PATH, MEANS FOR COMBINING THE OUTPUT SIGNALS OF SAID FIRST AND THIRD PATHS, MEANS FOR COMBINING THE OUTPUT SIGNALS OF SAID SECOND AND FOURTH PATHS, MEANS FOR COMBINING THE COMBINED OUTPUT SIGNALS AT A RESIDUE OUTPUT TERMINAL SO THAT THE TRANSFER CHARACTERISTIC BETWEEN THE ANALOG INPUT TERMINAL AND THE RESIDUE OUTPUT TERMINAL IS A DOUBLE V-SHAPED FULL WAVE RECTIFIER TRANSFER CHARACTERISTIC, AND MEANS FOR COMBINING THE ANALOG SIGNALS FROM SAID SECOND AND FOURTH PATHS TO PRODUCE A SECOND DIGIT OUTPUT SIGNAL.
Claim 2
Dependent Claim
364 words
AN ENCODING STAGE FOR A STAGE-BY-STAGE ENCODER WHICH COMPRISES, IN COMBINATION, AN AMPLIFIER HAVING AN INPUT TERMINAL AND AN OUTPUT TERMINAL, A SIGNAL INPUT TERMINAL CONNECTED TO SAID AMPLIFIER INPUT TERMINAL, A DIGIT OUTPUT TERMINAL AT WHICH A FIRST DIGIT OUTPUT SIGNAL IS OBTAINED CONNECTED TO SAID AMPLIFIER OUTPUT TERMINALS, TWO DIODES, A FIRST OF SAID DIODES HAVING ITS CATHODE CONNECTED TO THE OUTPUT TERMINAL OF SAID AMPLIFIER AND THE SECOND OF SAID DIODES HAVING ITS ANODE CONNECTED TO THE OUTPUT TERMINAL OF SAID AMPLIFIER, FIRST AND SECOND FEEDBACK PATHS CONNECTED BETWEEN SAID AMPLIFIER INPUT TERMINAL AND THE ANODE OF SAID FIRST DIODE, EACH OF SAID FEEDBACK PATHS COMPRISING THE SERIES COMBINATION OF A DIODE AND A RESISTANCE WITH THE CATHODE IN THE FIRST PATH POLED TO CONDUCT CURRENT IN THE OPPOSITE DIRECTION FROM THE DIODE IN SAID SECOND PATH, THIRD AND FOURTH FEEDBACK PATHS EACH COMPRISING THE SERIES COMBINATION OF A DIODE AND A RESISTANCE CONNECTED BETWEEN SAID AMPLIFIER INPUT TERMINAL AND THE CATHODE OF SAID DIODE WHOSE ANODE IS CONNECTED TO THE AMPLIFIER OUTPUT TERMINAL, THE DIODE IN SAID THIRD FEEDBACK PATH BEING POLED TO CONDUCT CURRENT IN THE OPPOSITE DIRECTION FROM THE DIODE IN SAID FOURTH FEEDBACK PATH, MEANS FOR DERIVING A FIRST ANALOG CURRENT SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE OF SAID FIRST FEEDBACK PATH, MEANS FOR DERIVING A SECOND ANALOG SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE OF SAID SECOND PATH, MEANS FOR DERIVING A THIRD ANALOG SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE OF SAID THIRD PATH, MEANS FOR DERIVING A FOURTH ANALOG SIGNAL FROM THE JUNCTION OF SAID RESISTANCE AND SAID DIODE IN SAID FOURTH FEEDBACK PATH, MEANS FOR COMBINING THE OUTPUT SIGNALS OF SAID FIRST AND THIRD PATHS, MEANS FOR COMBINING THE OUTPUT SIGNALS OF SAID SECOND AND FOURTH PATHS, MEANS FOR COMBINING THE COMBINED OUTPUT SIGNALS AT A RESIDUE OUTPUT TERMINAL SO THAT THE TRANSFER CHARACTERISTIC BETWEEN THE ANALOG INPUT TERMINAL AND THE RESIDUE OUTPUT TERMINAL IS A DOUBLE V-SHAPED FULL WAVE RECTIFIER TRANSFER CHARACTERISTIC, AND MEANS FOR COMBINING THE ANALOG SIGNALS FROM SAID SECOND AND FOURTH PATHS TO PRODUCE A SECOND DIGIT OUTPUT SIGNAL.
References Cited (Backward Citations)
US3161868A
Cited
US3329950A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1972-05-26 | 1972-11-25 | 1973-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1976-05-26 | 1976-11-25 | 1977-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1980-05-26 | 1980-11-25 | 1981-05-27 | $7700.00 | Window Closed / Lapsed |