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US3582676A
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Pulse length normalizing and short pulse eliminating circuit
Assignee: Bendix Corp
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Filing: 1968-09-24
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Granted: 1971-06-01
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Expires: 1988-09-24
Abstract
Abstract A differentiating circuit and an integrating circuit are combined in a logic gate to suppress transmission of pulses whenever an effective output appears from either circuit. The time constant of the differentiator determines minimum length and that of the integrator determines maximum length of transmitted pulses.
Inventors
- 👤 Erik Rosenbaum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:25
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/74; G01S13/76; G01S13/78; G01S13/781; G01S13/784; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
142 words
A short pulse eliminating and pulse length normalizing circuit comprising: input means to which pulses to be tested and normalized are applied, means for differentiating the output of said input means, said differentiating means providing an effective output for a time equal to the length of pulses to be eliminated, means for integrating the output of said input means, said integrating means providing an effective output after the lapse of a fixed time from the appearance of an output from said input means; gate means to which said pulses to be tested and normalized are applied, said gate being controlled by said integrating means and said differentiating means to block transmission of said pulses whenever an effective output appears from either of said last named means; and means applying pulses transmitted by said gate to said input means in positive feedback relationship.
Claim 2
Dependent Claim
142 words
A short pulse eliminating and pulse length normalizing circuit comprising: input means to which pulses to be tested and normalized are applied, means for differentiating the output of said input means, said differentiating means providing an effective output for a time equal to the length of pulses to be eliminated, means for integrating the output of said input means, said integrating means providing an effective output after the lapse of a fixed time from the appearance of an output from said input means; gate means to which said pulses to be tested and normalized are applied, said gate being controlled by said integrating means and said differentiating means to block transmission of said pulses whenever an effective output appears from either of said last named means; and means applying pulses transmitted by said gate to said input means in positive feedback relationship.
Claim 3
Dependent Claim
28 words
A circuit as claimed in claim 1 wherein said gate means includes pulse stretching means for prolonging the duration of said pulses to be transmitted by said gate.
Claim 4
Dependent Claim
21 words
A circuit as claimed in claim 1 wherein said input means is comprised by a logic gate of the OR type.
Claim 5
Dependent Claim
31 words
A circuit as claimed in claim 1 wherein the outputs of said differentiating and said integrating means are combined in a logic gate the output of which controls said gate means.
Claim 6
Dependent Claim
16 words
A circuit as claimed in claim 4 wherein said logic gate is of the NOR type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |