Patent US3577128A successfully refreshed from Google Patents.
US3577128A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing clock system
Assignee: International Business Machines Corp
•
Filing: 1969-01-14
•
Granted: 1971-05-04
•
Expires: 1989-01-14
Abstract
Abstract In a data processing system, apparatus for synchronizing a slave clock in an input/output device with a master clock in a central processing unit. A set of clock signals from a CPU are received in parallel, converted to serial and pulses are generated in response to the leading and trailing edge of each of the series of signals. The series of pulses is then delayed and shaped to drive a slaved I/O clock. A delay line is adjusted so that the total equivalent system delay is equal to an integral number of CPU pulse durations.
Inventors
- 👤 Tony N Criscimagna
- 👤 Robert J Fournier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:09
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G04; G04G; G04G7/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
179 words
Apparatus for synchronizing a first set of periodic timing signals from a first device with a second set of periodic timing signals from a second device comprising: combining means for combining said first set of timing signals to form a series of signals spaced in time, wherein each of said series of signals has a leading edge and a trailing edge; generating means connected to the output of said combining means for generating a series of impulses responsive to said leading and trailing edges of each of said series of signals; delay means, connected to the output of said generating means for delaying said series of impulses a duration of time equal to N timing signal durations, of said first set of timing signals, minus all accumulated transmission time delays between said first device and said second device where N is an integer; counter means for generating said second set of periodic timing signals in response to and in synchronism with said delayed series of impulses thereby achieving synchronization between said first and second sets of periodic timing signals.
Claim 2
Dependent Claim
179 words
Apparatus for synchronizing a first set of periodic timing signals from a first device with a second set of periodic timing signals from a second device comprising: combining means for combining said first set of timing signals to form a series of signals spaced in time, wherein each of said series of signals has a leading edge and a trailing edge; generating means connected to the output of said combining means for generating a series of impulses responsive to said leading and trailing edges of each of said series of signals; delay means, connected to the output of said generating means for delaying said series of impulses a duration of time equal to N timing signal durations, of said first set of timing signals, minus all accumulated transmission time delays between said first device and said second device where N is an integer; counter means for generating said second set of periodic timing signals in response to and in synchronism with said delayed series of impulses thereby achieving synchronization between said first and second sets of periodic timing signals.
Claim 3
Dependent Claim
139 words
Apparatus according to claim 1, wherein: said first device is a central processor unit of a data processing system; said second device is an input/output unit of a data processing system; said combining means is a logical OR circuit; and said generating means comprises a plurality of single shot monostable circuits, a first of which generates an impulse in response to the leading edge of each of said series of signals and a second of which generates a series of impulses in response to the trailing edge of eAch of said series of signals; and said counter means comprises a plurality of gated bistable flip-flop circuits each of which changes state from the off condition to the on condition in response to a change in the state from the on condition to the off condition of the preceding stage.
Claim 4
Dependent Claim
22 words
Apparatus according to claim 1, wherein said first set of timing signals comprises alternate pulses from a master set of timing signals.
References Cited (Backward Citations)
US3188484A
Cited
US3214695A
Cited
US3247491A
Cited
US3333246A
Cited
US3343136A
Cited
US3488478A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-03 | 1974-11-02 | 1975-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-03 | 1978-11-02 | 1979-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-03 | 1982-11-02 | 1983-05-04 | $7700.00 | Window Closed / Lapsed |