Pulse synchronizer

Claim 1

A SYNCHRONIZING CIRCUIT FOR SYNCHRONIZING PULSE SIGNALS WITH SUBSTANTIALLY EVENLY SPACED RECURRING TIMING PULSES OF PREDETERMINED PULSE WIDTH, COMPRISING A BISTABLE CIRCUIT HAVING FIRST AND SECOND STATES AND NORMALLY ARRANGED IN SAID FIRST STATE, A SEPARATE GATING CIRCUIT CONNECTED TO BE RESPONSIVE TO THE COINCIDENCE OF A PULSE SIGNAL TO BE SYNCHRONIZED AND A TIMING PULSE DELIVERED THERETO FOR FORMING AN OUTPUT SIGNAL, SAID BISTABLE CIRCUIT BEING CONNECTED TO BE RESPONSIVE TO SAID OUTPUT SIGNAL FOR SWITCHING INTO SAID SECOND STATE, A SWITCHING CIRCUIT AND A TIME DELAY CIRCUIT FOR CONTROLLING THE SWITCHING CIRCUIT, SAID TIME DELAY CIRCUIT BEING RESPONSIVE TO THE OCCURRENCE OF THE CHANGE IN STATE OF THE BISTABLE CIRCUIT AND ARRANGED WITH A TIME DELAY SUCH THAT THE SWITCHING CIRCUIT IS SWITCHED TO FORM A SYNCHRONIZED PULSE BEGINNING WITH THE TERMINATION OF THE TIMING PULSE CAUSING THE OUTPUT SIGNAL FROM THE GATING CIRCUIT AND ENDING DURING THE TIME INTERVAL BEGINNING WITH THE TERMINATION OF THE NEXT SEQUENTIAL TIMING PULSE AND ENDING WITH THE BEGINNING OF THE SECOND TIMING PULSE FOLLOWING THE TIMING PULSE CAUSING THE OUTPUT SIGNAL FROM THE TIMING CIRCUIT FOR THEREBY FORMING A SYNCHRONIZED PULSE SIMULTANTEOUSLY WITH A SINGLE ONE OF THE TIMING PULSES DELIVERED TO SAID GATING CIRCUIT.