Patent US3566155A successfully refreshed from Google Patents.
US3566155A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit synchronization system
Assignee: TDK Micronas GmbH
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Filing: 1968-06-25
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Granted: 1971-02-23
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Expires: 1988-06-25
Abstract
Abstract A flip-flop is coupled to a code signal source and a bit clock source. Logic and amplifier circuitry cooperate with the flipflop to produce two oppositely varying width modulated pulses having opposite polarity. An integrating filter algebraically combines the width modulated pulses to produce a control signal proportional to the phase relationship between the bits of the code signal and the clock bits. The control signal adjusts a voltage control led oscillator in the bit clock source to establish synchronization between the bits of the two signals. The integrating filter has a first time constant enabling rapid synchronization and a second time constant to maintain the value of the control signal during long fades of the code signal.
Inventors
- 👤 Samuel J Demaio
- 👤 Arthur H Magnus
- 👤 James G Dunn
- 👤 John Granlund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:09
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
282 words
A system to generate an output signal proportional to the phase relationship of a first pulse signal and a second pulse signal comprising: a first source of said first pulse signal; a second source of said second pulse signal; first means coupled to said first and second sources to compare the phase relationship of said first and second pulse signals; second means coupled to said first means to produce a third pulse signal of one polarity having a first width variation dependent on the phase relationship of said first and second pulse signals; third means coupled to said first means to produce a fourth pulse signal of a polarity opposite to said one polarity having a second width variation dependent on the phase relationship of said first and second signals opposite said first width variation; and fourth means coupled to said second and third means responsive to said third and fourth pulse signals to provide said output signal; said first means including: inverting means coupled to said first source, and a flip-flop having its ''''1'''' input coupled to said inverting means and its ''''0'''' input coupled to said second source; said second means including: first amplifier means coupled to the ''''1'''' output of said flip-flop to produce said third signal; said third means including: monostable means coupled to said inverting means, logic circuit means coupled to the ''''0'''' output of said flip-flop and said monostable means, and second amplifier means coupled to said logic circuit means to produce said fourth signal; and said fourth means including: integrating means coupled to said first and second amplifier means to provide said output signal in response to the duration of said third and fourth signals.
Claim 2
Independent Claim
282 words
A system to generate an output signal proportional to the phase relationship of a first pulse signal and a second pulse signal comprising: a first source of said first pulse signal; a second source of said second pulse signal; first means coupled to said first and second sources to compare the phase relationship of said first and second pulse signals; second means coupled to said first means to produce a third pulse signal of one polarity having a first width variation dependent on the phase relationship of said first and second pulse signals; third means coupled to said first means to produce a fourth pulse signal of a polarity opposite to said one polarity having a second width variation dependent on the phase relationship of said first and second signals opposite said first width variation; and fourth means coupled to said second and third means responsive to said third and fourth pulse signals to provide said output signal; said first means including: inverting means coupled to said first source, and a flip-flop having its ''''1'''' input coupled to said inverting means and its ''''0'''' input coupled to said second source; said second means including: first amplifier means coupled to the ''''1'''' output of said flip-flop to produce said third signal; said third means including: monostable means coupled to said inverting means, logic circuit means coupled to the ''''0'''' output of said flip-flop and said monostable means, and second amplifier means coupled to said logic circuit means to produce said fourth signal; and said fourth means including: integrating means coupled to said first and second amplifier means to provide said output signal in response to the duration of said third and fourth signals.
Claim 3
Independent Claim
383 words
A system to generate an output signal proportional to the phase relationship of a first pulse signal and a second pulse signal comprising: a first source of said first pulse signal; a second source of said second pulse signal; first means coupled to said first and second sources to compare the phase relationship of said first and second pulse signals; second means coupled to said first means to produce a third pulse signal of one polarity having a first width variation dependent on the phase relationship of said first and second pulse signals; third means coupled to said first means to produce a fourth pulse signal of a polarity opposite to said one polarity having a second width variation dependent on the phase relationship of said first and second signals opposite said first width variation; and fourth means coupled to said second and third means responsive to said third and fourth pulse signals to provide said output signal; said first means including: first inverting means coupled to said first source; second inverting means coupled to said sEcond source; and a flip-flop having its ''''1'''' input coupled to said first inverting means and its ''''0'''' input coupled to said second inverting means; said second means including: first logic circuit means coupled to the ''''1'''' output of said flip-flop; and first amplifier means coupled to said first logic circuit means to produce said third signal; said third means including: second logic circuit means coupled to the ''''1'''' output of said flip-flop and said first source; and second amplifier means coupled to said second logic circuit means to produce said fourth signal; and said fourth means including: integrating means having capacitive means to provide said output signal; a first constant current source coupled to said capacitive means and the appropriate one of said first and second amplifier means responsive to the duration of the associated one of said third and fourth signals to control the conduction of said first current source to charge said capacitive means; and a second constant current source coupled to said capacitive means and the other of said first and second amplifier means responsive to the duration of the associated one of said third and fourth signals to control the conduction of said second current source to discharge of said capacitive means.
Claim 4
Independent Claim
383 words
A system to generate an output signal proportional to the phase relationship of a first pulse signal and a second pulse signal comprising: a first source of said first pulse signal; a second source of said second pulse signal; first means coupled to said first and second sources to compare the phase relationship of said first and second pulse signals; second means coupled to said first means to produce a third pulse signal of one polarity having a first width variation dependent on the phase relationship of said first and second pulse signals; third means coupled to said first means to produce a fourth pulse signal of a polarity opposite to said one polarity having a second width variation dependent on the phase relationship of said first and second signals opposite said first width variation; and fourth means coupled to said second and third means responsive to said third and fourth pulse signals to provide said output signal; said first means including: first inverting means coupled to said first source; second inverting means coupled to said sEcond source; and a flip-flop having its ''''1'''' input coupled to said first inverting means and its ''''0'''' input coupled to said second inverting means; said second means including: first logic circuit means coupled to the ''''1'''' output of said flip-flop; and first amplifier means coupled to said first logic circuit means to produce said third signal; said third means including: second logic circuit means coupled to the ''''1'''' output of said flip-flop and said first source; and second amplifier means coupled to said second logic circuit means to produce said fourth signal; and said fourth means including: integrating means having capacitive means to provide said output signal; a first constant current source coupled to said capacitive means and the appropriate one of said first and second amplifier means responsive to the duration of the associated one of said third and fourth signals to control the conduction of said first current source to charge said capacitive means; and a second constant current source coupled to said capacitive means and the other of said first and second amplifier means responsive to the duration of the associated one of said third and fourth signals to control the conduction of said second current source to discharge of said capacitive means.
Claim 5
Independent Claim
252 words
A system to synchronize a local bit clock signal to received bits of a binary code signal comprising: a first source of said code signal; a second source of said clock signal; first means coupled to said first and second sources to compare the phase relationship of the bits of said code and clock signals; second means coupled to said first means to produce a first pulse signal of one polarity having a first width variation dependent on the phase relationship of the bits of said code and clock signals; third means coupled to said first means to produce a second pulse signal of a polarity opposite said one polarity having a second width variation dependent on the phase relationship of the bits of said code and clock signals opposite said first width variation; and fourth A system according to said second and third means and said second source responsive to said first and second pulse signals to produce a control signal for input to said second source to adjust the phase of the bits of said clock signal to establish and maintain synchronism between the bits of said code and clock signals; said fourth means including: an integrating means coupled to said second and third means and said second source having: fifth means to enable rapid production of said control signal to establish synchronism; and sixth means to maintain the value of said control signal when the amplitude of said code signal decreases to a value below a given amplitude level.
Claim 6
Independent Claim
252 words
A system to synchronize a local bit clock signal to received bits of a binary code signal comprising: a first source of said code signal; a second source of said clock signal; first means coupled to said first and second sources to compare the phase relationship of the bits of said code and clock signals; second means coupled to said first means to produce a first pulse signal of one polarity having a first width variation dependent on the phase relationship of the bits of said code and clock signals; third means coupled to said first means to produce a second pulse signal of a polarity opposite said one polarity having a second width variation dependent on the phase relationship of the bits of said code and clock signals opposite said first width variation; and fourth A system according to said second and third means and said second source responsive to said first and second pulse signals to produce a control signal for input to said second source to adjust the phase of the bits of said clock signal to establish and maintain synchronism between the bits of said code and clock signals; said fourth means including: an integrating means coupled to said second and third means and said second source having: fifth means to enable rapid production of said control signal to establish synchronism; and sixth means to maintain the value of said control signal when the amplitude of said code signal decreases to a value below a given amplitude level.
Claim 7
Dependent Claim
15 words
A system according to claim 3, wherein said sixth means includes a field effect transistor.
Claim 8
Dependent Claim
34 words
A system according to claim 3, wherein said first means includes bistable means having two inputs, one input being coupled to said first source and the other input being coupled to said second source.
Claim 9
Independent Claim
319 words
A system to synchronize a local bit clock signal to received bits of a binary code signal comprising: a first source of said code signal; a second source of said clock signal; first means coupled to said first and second sources to compare the phase relationship of the bits of said code and clock signals; second means coupled to said first means to produce a first pulse signal of one polarity having a first width variation dependent on the phase relationship of the bits of said code and clock signals; third means coupled to said first means to produce a second pulse signal of a polarity opposite said one polarity having a second width variation dependent on the phase relationship of the bits of said code and clock signals opposite said first width variation; and fourth means coupled to said second and third means and said second source responsive to said first and second pulse signals to produce a control signal for application to said second source to adjust the phase of the bits of said clock signal to establish and maintain synchronism between the bits of said code and clock signals; said first means including: inverting means coupled to said first source; and a flip-flop having its ''''1'''' input coupled to said inverting means and its ''''0'''' input coupled to said second source; said second means including: first amplifier means coupled to the ''''1'''' output of said flip-flop to produce said first pulse signals; said third means including: monostable means coupled to said inverting means; logic circuit means coupled to the ''''0'''' output of said flip-flop and said monostable means; and second amplifier means coupled to said logic circuit means to produce said second pulse signal; and said fourth means including: integrating means coupled to said first and second amplifier means to provide said control signal in response to the duration of said first and second pulse signals.
Claim 10
Independent Claim
319 words
A system to synchronize a local bit clock signal to received bits of a binary code signal comprising: a first source of said code signal; a second source of said clock signal; first means coupled to said first and second sources to compare the phase relationship of the bits of said code and clock signals; second means coupled to said first means to produce a first pulse signal of one polarity having a first width variation dependent on the phase relationship of the bits of said code and clock signals; third means coupled to said first means to produce a second pulse signal of a polarity opposite said one polarity having a second width variation dependent on the phase relationship of the bits of said code and clock signals opposite said first width variation; and fourth means coupled to said second and third means and said second source responsive to said first and second pulse signals to produce a control signal for application to said second source to adjust the phase of the bits of said clock signal to establish and maintain synchronism between the bits of said code and clock signals; said first means including: inverting means coupled to said first source; and a flip-flop having its ''''1'''' input coupled to said inverting means and its ''''0'''' input coupled to said second source; said second means including: first amplifier means coupled to the ''''1'''' output of said flip-flop to produce said first pulse signals; said third means including: monostable means coupled to said inverting means; logic circuit means coupled to the ''''0'''' output of said flip-flop and said monostable means; and second amplifier means coupled to said logic circuit means to produce said second pulse signal; and said fourth means including: integrating means coupled to said first and second amplifier means to provide said control signal in response to the duration of said first and second pulse signals.
Claim 11
Independent Claim
419 words
A system to synchronize a local bit clock signal to receive bits of a binary code signal comprising: a first source of said code signal; a second source of said clock signal; first means coupled to said first and second sources to compare the phase relationship of the bits of said code and clock signals; second means coupled to said first means to produce a first pulse signal of one polarity having a first width variation dependent on the phase relationship of the bits of said code and clock signals; third means coupled to said first means to produce a second pulse signal of a polarity opposite said one polarity having a second width variation dependent on the phase relationship of the bits of said code and clock signals opposite said first width variation; and fourth means coupled to said second and third means and said second source responsive to said first and second pulse signals to produce a control signal for application to said second source to adjust the phase of the bits of said clock signal to establish and maintain synchronism between the bits of said code and clock signals; said first means including: first inverting means coupled to said first source; second inverting means coupled to said second source; and a flip-flop having its ''''1'''' input coupled to said first inverting means and its ''''0'''' input coupled to said second inverting means; said second means including: first logic circuit means coupled to the ''''1'''' output of said flip-flop; and first amplifier means coupled to said first logic circuit means to produce said first pulse signal; said third means including: second logic circuit means coupled to the ''''1'''' output of said flip-flop and said first source; and second amplifier means coupled to said second logic circuit means to produce said second pulse signal; and said fourth means including: integrating means having capacitive means to provide said control signal; a first constant current source coupled to said capacitive means and the appropriate one of said first and second amplifier means responsive to the duration of the associated one of said first and second pulse signals to control the conduction of said first current source to charge said capacitive means; and a second constant source coupled to said capacitive means and the other of said first and second amplifier means responsive to the duration of the associated one of said first and second pulse signals to control the conduction of said second current source to discharge said capacitive means.
Claim 12
Independent Claim
419 words
A system to synchronize a local bit clock signal to receive bits of a binary code signal comprising: a first source of said code signal; a second source of said clock signal; first means coupled to said first and second sources to compare the phase relationship of the bits of said code and clock signals; second means coupled to said first means to produce a first pulse signal of one polarity having a first width variation dependent on the phase relationship of the bits of said code and clock signals; third means coupled to said first means to produce a second pulse signal of a polarity opposite said one polarity having a second width variation dependent on the phase relationship of the bits of said code and clock signals opposite said first width variation; and fourth means coupled to said second and third means and said second source responsive to said first and second pulse signals to produce a control signal for application to said second source to adjust the phase of the bits of said clock signal to establish and maintain synchronism between the bits of said code and clock signals; said first means including: first inverting means coupled to said first source; second inverting means coupled to said second source; and a flip-flop having its ''''1'''' input coupled to said first inverting means and its ''''0'''' input coupled to said second inverting means; said second means including: first logic circuit means coupled to the ''''1'''' output of said flip-flop; and first amplifier means coupled to said first logic circuit means to produce said first pulse signal; said third means including: second logic circuit means coupled to the ''''1'''' output of said flip-flop and said first source; and second amplifier means coupled to said second logic circuit means to produce said second pulse signal; and said fourth means including: integrating means having capacitive means to provide said control signal; a first constant current source coupled to said capacitive means and the appropriate one of said first and second amplifier means responsive to the duration of the associated one of said first and second pulse signals to control the conduction of said first current source to charge said capacitive means; and a second constant source coupled to said capacitive means and the other of said first and second amplifier means responsive to the duration of the associated one of said first and second pulse signals to control the conduction of said second current source to discharge said capacitive means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |