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US3560809A
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Variable capacitance rectifying junction diode
Assignee: Hitachi Ltd
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Filing: 1969-02-27
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Granted: 1971-02-02
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Expires: 1989-02-27
Abstract
Abstract A variable capacitance diode comprising a super abrupt junction therein, said diode comprising a semiconductor wafer including a semiconductor region having a graded impurity concentration, and a metal layer deposited on one surface of said semiconductor region to form a surface barrier at said one surface of the semiconductor region.
Inventors
- 👤 Hajime Terakado
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:45
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/049; Y10S148/139
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
34 words
The element according to claim 1, wherein said substrate is of N-type silicon crystal, and said electrode comprises at least a metal selected from the group consisting of chromium, titanium, tantalum, nickel and vanadium.
Claim 2
Dependent Claim
61 words
The element according to claim 1, wherein said substrate is of N-type silicon crystal, and said electrode comprises a metal layer including a metal selected from the group consisting of tungsten and molybdenum and a thin silicide layer of silicon and said metal interposed between said metal layer and said first semiconductor region forming a rectifying surface barrier with the substrate.
Claim 3
Dependent Claim
188 words
A semiconductor device comprising: a semiconductor substrate of high conductivity silicon: a semiconductor layer of high resistivity silicon, said layer having the same conductivity type as that as of said substrate and being formed in contact with said substrate; a diffused region of silicon material formed in contact with said semiconductor layer and spaced from said substrate, the thickness of the layer between said diffused region and said substrate being in the range of from 1.5 Mu to 4.5 Mu said diffused region being of the same conductivity type as that of said substrate, the impurity concentration in the diffused region decreasing in the direction toward said semiconductor layer and being higher than that of a said semiconductor at the interface with said semiconductor layer; an insulating layer covering said diffused region and having a hole; a silicide layer formed in a said hole in said insulating layer and forming a rectifying surface barrier with said diffused region, said silicide layer including a metal selected from the group consisting of tungsten and molybdenum; and an electrode connected to said silicide layer through said holes in said insulating layer.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-01 | 1974-08-03 | 1975-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-01 | 1978-08-03 | 1979-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-01 | 1982-08-03 | 1983-02-02 | $7700.00 | Window Closed / Lapsed |